ISE综合错误：Failed to synthesize logic for signal
最近用ISE写个频率计的verilog程序 刚学ISE，感觉很多综合时限制很多，比quartus难用很多 下面这个报错弄了很久没发现错在哪，在quartus里综合能通过，但在ISE里综合就不行，能哪位大虾能指点一二吗？不胜感激！`timescale 1ns / 1ps
module plj(clk,clk_test,sw0,sw1,rst,out_wei,out_duan,miao);
input clk,rst,clk_test,sw0,sw1;
output reg out_wei;
output reg out_duan;
output reg miao;
reg count2;
reg ge,shi,bai,qian,p_10K,p_100K,p_M,p_10M,p_100M,s_ge,s_shi,s_bai,s_qian,s_10K,s_100K,s_M,s_10M,s_100M;
reg flag=0;
reg saomiao=0;
reg duan;
always@(posedge clk)
begin if(!rst) begin count2<=0;flag<=0; end
else begin count2<=count2+1;
if(count2==50000000) begin flag<=1;miao<=1;end
if(count2>=100000000)begin flag<=0;count2<=0;miao<=0;end
end
end
always@(posedge clk_test or negedge rst)
begin if(!rst) begin ge<=0;shi<=0;bai<=0;qian<=0;p_10K<=0;p_100K<=0;p_M<=0;p_10M<=0;p_100M<=0; end
else if(count2==60000000) begin ge<=0;shi<=0;bai<=0;qian<=0;p_10K<=0;p_100K<=0;p_M<=0;p_10M<=0;p_100M<=0;end
else if(!flag)
begin
ge<=ge+1;
if(ge==9) begin ge<=0;shi<=shi+1;
if(shi==9) begin shi<=0;bai<=bai+1;
if(bai==9) begin bai<=0;qian<=qian+1;
if(qian==9) begin qian<=0;p_10K<=p_10K+1;
if(p_10K==9)begin p_10K<=0;p_100K<=p_100K+1;
if(p_100K==9) begin p_100K<=0;p_M<=p_M+1;
if(p_M==9) begin p_M<=0;p_10M<=p_10M+1;
if(p_10M==9) begin p_10M<=0;p_100M<=p_100M+1; end
end end end end end end end end
else begin ge<=ge;shi<=shi;bai<=bai;qian<=qian;p_10K<=p_10K;p_100K<=p_100K;p_M<=p_M;p_10M<=p_10M;p_100M<=p_100M; end
end
always@(posedge clk or negedge rst)
begin if(!rst) saomiao<=0;
else begin saomiao<=saomiao+1;
if(saomiao==1000000) saomiao<=0;
end
end
always@(posedge clk or negedge rst)
begin if(!rst) begin s_ge<=0;s_shi<=0;s_bai<=0;s_qian<=0;s_10K<=0;s_100K<=0;s_M<=0;s_10M<=0;s_100M<=0; end
else if(count2==50000000) begin s_ge<=ge;s_shi<=shi;s_bai<=bai;s_qian<=qian;s_10K<=p_10K;s_100K<=p_100K;s_M<=p_M;s_10M<=p_10M;s_100M<=p_100M;
end
end
always@(posedge clk or negedge rst)
begin
if(!rst) begin
case(saomiao)
0:begin out_wei<=4'b1000;
duan<=0;
end
250000:begin out_wei<=4'b0100;
duan<=1;
end
500000:begin out_wei<=4'b0010;
duan<=2;
end
750000:begin out_wei<=4'b0001;
duan<=3;
end
endcase
end
else if((sw1==0)&&(sw0==0))
begin case(saomiao)
0:begin out_wei<=4'b1000;
duan<=s_ge;
end
250000:begin out_wei<=4'b0100;
duan<=s_shi;
end
500000:begin out_wei<=4'b0010;
duan<=s_bai;
end
750000:begin out_wei<=4'b0001;
duan<=s_qian;
end
default:begin out_wei<=out_wei;
duan<=duan;
end
endcase
end
else if((sw1==0)&&(sw0==1)) begin
case(saomiao)
0:begin out_wei<=4'b1000;
duan<=s_10K;
end
250000:begin out_wei<=4'b0100;
duan<=s_100K;
end
500000:begin out_wei<=4'b0010;
duan<=s_M;
end
750000:begin out_wei<=4'b0001;
duan<=s_10M;
end
default:begin out_wei<=out_wei;
duan<=duan;
end
endcase
end
else if((sw1==1)&&(sw0==1)) begin
case(saomiao)
0:begin out_wei<=4'b1000;
duan<=s_100M;
end
250000:begin out_wei<=4'b0100;
duan<=0;
end
500000:begin out_wei<=4'b0010;
duan<=0;
end
750000:begin out_wei<=4'b0001;
duan<=0;
end
default:begin out_wei<=out_wei;
duan<=duan;
end
endcase
end
end
always@(posedge clk)
case(duan)
0ut_duan<=8'h3f;
1ut_duan<=8'h06;
2ut_duan<=8'h5b;
3:out_duan<=8'h4f;
4:out_duan<=8'h66;
5:out_duan<=8'h6d;
6:out_duan<=8'h7d;
7:out_duan<=8'h07;
8:out_duan<=8'h7f;
9:out_duan<=8'h6f;
//default:out_duan<=8'hff;
endcase
endmodule
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