16bit-spi-master的问题 (amobbs.com 阿莫电子技术论坛) -

yl604922959 发表于 2010-7-19 11:21:53

16bit-spi-master的问题

//为什么只能写出去，但是读进来的都是0呢？
module spimaster(rst,clk,rd,wr,datain,spics,spiclk,spido,spidi,dataout,test
);
input rst;
input clk;
input rd;
input wr;
input spidi;
input datain;

output spics;
output spiclk;
output spido;
output dataout;
output test;

reg spics;
reg spiclk;
reg spido;
reg dstate,dsend,dreceive,dataout;
reg spistate;
reg test;

parameter idle=2'b00;
parameter send_data=2'b01;
parameter receive_data=2'b10;

initial test <= 0;

always @(posedge clk)
begin
if(rst==0)
begin
spistate<=2'b00;
   spics<=1'b1;
   spiclk<=1'b1;
   spido<=1'b0;
   dstate<=8'd0;
test <= 0;
end
else begin
case (spistate)
2'b00:
begin
spics<=1'b1;
spiclk<=1'b1;
spido<=1'b0;
if((wr==1'b0)&&(rd==1'b1))
begin
spistate<=send_data;
dstate<=8'd0;
dsend<=datain;
end
else if((wr==1'b1)&&(rd==1'b0))
begin
spistate<=receive_data;
dstate<=8'd0;
end
end

2'b01:
begin
case(dstate)
8'd0:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=1'b0;
dstate<=8'd1;
end
8'd1:
begin
test <= 1;
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd2;
end
8'd2:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=dsend;
dstate<=8'd3;
end
8'd3:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd4;
end
8'd4:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd5;
end
8'd5:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=dsend;
dstate<=8'd6;
end
8'd6:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd7;
end
8'd7:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd8;
end
8'd8:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=dsend;
dstate<=8'd9;
end
8'd9:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd10;
end
8'd10:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd11;
end
8'd11:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=dsend;
dstate<=8'd12;
end
8'd12:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd13;
end
8'd13:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd14;
end
8'd14:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=dsend;
dstate<=8'd15;
end
8'd15:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd16;
end
8'd16:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd17;
end
8'd17:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=dsend;
dstate<=8'd18;
end
8'd18:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd19;
end
8'd19:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd20;
end
8'd20:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=dsend;
dstate<=8'd21;
end
8'd21:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd22;
end
8'd22:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd23;
end
8'd23:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=dsend;
dstate<=8'd24;
end
8'd24:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd25;
end
8'd25:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd26;
end
8'd26:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=dsend;
dstate<=8'd27;
end
8'd27:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd28;
end
8'd28:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd29;
end
8'd29:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=dsend;
dstate<=8'd30;
end
8'd30:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd31;
end
8'd31:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd32;
end
8'd32:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=dsend;
dstate<=8'd33;
end
8'd33:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd34;
end
8'd34:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd35;
end
8'd35:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=dsend;
dstate<=8'd36;
end
8'd36:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd37;
end
8'd37:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd38;
end
8'd38:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=dsend;
dstate<=8'd39;
end
8'd39:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd40;
end
8'd40:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd41;
end
8'd41:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=dsend;
dstate<=8'd42;
end
8'd42:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd43;
end
8'd43:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd44;
end
8'd44:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=dsend;
dstate<=8'd45;
end
8'd45:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd46;
end
8'd46:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend;
dstate<=8'd47;
end
8'd47:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=dsend;
dstate<=8'd48;
end
8'd48:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=dsend;
dstate<=8'd49;
test <= 0;
end

8'd49:
begin
spics<=1'b1;
spiclk<=1'b1;
spido<=1'b0;
dstate<=8'd0;
spistate<=idle;
end

endcase
end

2'b10:
begin
case(dstate)
8'd0:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=1'b0;
dstate<=8'd1;
test<=1'b1;

end
8'd1:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=1'b0;
dstate<=8'd2;
end
8'd2:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=1'b0;
dstate<=8'd3;
end
8'd3:
begin
spics<=1'b0;
spiclk<=1'b1;
dstate<=8'd4;
end
8'd4:
begin
spics<=1'b0;
spiclk<=1'b0;
dreceive<=spidi;
spido<=1'b0;
dstate<=8'd5;
end
8'd5:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=1'b0;
dstate<=8'd6;
end
8'd6:
begin
spics<=1'b0;
spiclk<=1'b0;
dreceive<=spidi;
spido<=1'b0;
dstate<=8'd7;
end
8'd7:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=1'b0;
dstate<=8'd8;
end
8'd8:
begin
spics<=1'b0;
spiclk<=1'b0;
dreceive<=spidi;
spido<=1'b0;
dstate<=8'd9;
end
8'd9:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=1'b0;
dstate<=8'd10;
end
8'd10:
begin
spics<=1'b0;
spiclk<=1'b0;
dreceive<=spidi;
spido<=1'b0;
dstate<=8'd11;
end
8'd11:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=1'b0;
dstate<=8'd12;
end
8'd12:
begin
spics<=1'b0;
spiclk<=1'b0;
dreceive<=spidi;
spido<=1'b0;
dstate<=8'd13;
end
8'd13:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=1'b0;
dstate<=8'd14;
end
8'd14:
begin
spics<=1'b0;
spiclk<=1'b0;
dreceive<=spidi;
spido<=1'b0;
dstate<=8'd15;
end
8'd15:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=1'b0;
dstate<=8'd16;
end
8'd16:
begin
spics<=1'b0;
spiclk<=1'b0;
dreceive<=spidi;
spido<=1'b0;
dstate<=8'd17;
end
8'd17:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=1'b0;
dstate<=8'd18;
end
8'd18:
begin
spics<=1'b0;
spiclk<=1'b0;
dreceive<=spidi;
spido<=1'b0;
dstate<=8'd19;
end
8'd19:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=1'b0;
dstate<=8'd20;
end
8'd21:
begin
spics<=1'b0;
spiclk<=1'b0;
dreceive<=spidi;
spido<=1'b0;
dstate<=8'd22;
end
8'd22:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=1'b0;
dstate<=8'd23;
end
8'd23:
begin
spics<=1'b0;
spiclk<=1'b0;
dreceive<=spidi;
spido<=1'b0;
dstate<=8'd24;
end
8'd24:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=1'b0;
dstate<=8'd25;
end
8'd25:
begin
spics<=1'b0;
spiclk<=1'b0;
dreceive<=spidi;
spido<=1'b0;
dstate<=8'd26;
end
8'd26:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=1'b0;
dstate<=8'd27;
end
8'd28:
begin
spics<=1'b0;
spiclk<=1'b0;
dreceive<=spidi;
spido<=1'b0;
dstate<=8'd29;
end
8'd29:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=1'b0;
dstate<=8'd30;
end
8'd30:
begin
spics<=1'b0;
spiclk<=1'b0;
dreceive<=spidi;
spido<=1'b0;
dstate<=8'd31;
end
8'd31:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=1'b0;
dstate<=8'd32;
end
8'd32:
begin
spics<=1'b0;
spiclk<=1'b0;
dreceive<=spidi;
spido<=1'b0;
dstate<=8'd33;
end
8'd33:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=1'b0;
dstate<=8'd34;
end
8'd34:
begin
spics<=1'b0;
spiclk<=1'b0;
dreceive<=spidi;
spido<=1'b0;
dstate<=8'd35;
end
8'd35:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=1'b0;
dstate<=8'd36;
end
8'd36:
begin
spics<=1'b0;
spiclk<=1'b0;
dreceive<=spidi;
spido<=1'b0;
dstate<=8'd37;
end
8'd37:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=1'b1;
dstate<=8'd38;
dataout<=dreceive;
end
8'd38:
begin
spics<=1'b1;
spiclk<=1'b1;
spido<=1'b1;
dstate<=8'd0;
spistate<=2'b00;
end
endcase
end
default:
begin
spics<=1'b1;
spiclk<=1'b1;
spido<=1'b0;
spistate<=idle;
end

endcase
end
end
endmodule

yl604922959 发表于 2010-7-19 11:45:28

对啊，还有，我把5v的单片机的输出，即miso和FPGA的miso直接接到了一起了，会不会是因为3.3的电平和5v的电平标准不一样而把FPGA的端口晒坏了呢？

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16bit-spi-master的问题