初学者 请教verilog设计8路彩灯控制器的程序
序号 L0 L1 L2 L3 L4 L5 L6 L70 1 1 1 1 1 1 1 0
1 0 1 1 1 1 1 1 1
2 1 0 1 1 1 1 1 1
3 1 1 0 1 1 1 1 1
4 1 1 1 0 1 1 1 1
5 1 1 1 1 0 1 1 1
6 1 1 1 1 1 0 1 1
7 1 1 1 1 1 1 0 1
8 1 1 1 1 1 1 1 0
9 1 1 1 1 1 1 1 1
10 0 1 1 1 1 1 1 1
11 0 0 1 1 1 1 1 1
12 0 0 0 1 1 1 1 1
13 0 0 0 0 1 1 1 1
14 0 0 0 0 0 1 1 1
15 0 0 0 0 0 0 1 1
16 0 0 0 0 0 0 0 1
17 0 0 0 0 0 0 0 0
18 1 0 0 0 0 0 0 0
19 1 1 0 0 0 0 0 0
20 1 1 1 0 0 0 0 0
21 1 1 1 1 0 0 0 0
22 1 1 1 1 1 0 0 0
23 1 1 1 1 1 1 0 0
24 1 1 1 1 1 1 1 0
25 1 0 0 0 0 0 0 0
26 0 1 0 0 0 0 0 0
27 0 0 1 0 0 0 0 0
28 0 0 0 1 0 0 0 0
29 0 0 0 0 1 0 0 0
30 0 0 0 0 0 1 0 0
31 0 0 0 0 0 0 1 0
32 0 0 0 0 0 0 0 1
以上为16个灯的亮灭顺序 module caideng(clk,light,res);
input clk,res;
output light;
reg state;
reg light;
parameter
FIRST=4'd0,
A=4'd1,B=4'd2,
C=4'd3,D=4'd4,
E=4'd5,F=4'd6,
G=4'd7,H=4'd8,
I=4'd9,J=4'd10,
K=4'd11, L=4'd12;
always @(posedge clk)
begin
if(!res)
begin
state=FIRST;
end
else
casex(state)
FIRST:state<=A;
A:begin
light=4'b1000;
state<=B;
end
B:begin
light=4'b1100;
state<=C;
end
C:begin
light=4'b1110;
state<=D;
end
D:begin
light=4'b1111;
state<=E;
end
E:begin
light=4'b1110;
state<=F;
end
F:begin
light=4'b1100;
state<=G;
end
G:begin
light=4'b1000;
state<=H;
end
H:begin
light=4'b0000;
state<=I;
end
I:begin
light=4'b1001;
state<=J;
end
J:begin
light=4'b1111;
state<=K;
end
K:begin
light=4'b1001;
state<=L;
end
L:begin
light=4'b0000;
state<=A;
end
default:state=FIRST;
endcase
end
endmodule
需要在这个基础上改下，哪位帮忙看下？
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