跪求用vhdl生成正弦波的问题
小弟毕设要做基于fpga的任意波形发生器，板子用的周立功的030，开发软件用的libero 8.5，其中正弦波模块就是显示不出来，永远红线~~~~~郁闷，求大虾帮忙啊！原程序如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sin_gen is
port (clk,clr:in std_logic;
d:out std_logic_vector(7 downto 0));
end sin_gen;
architecture a of sin_gen is
begin
process(clk,clr)
variable num:integer range 0 to 63;
begin
if clr='0' then
d<="00000000" ;
elsif clk'event and clk='1' then
if num=63 then
num:=0;
else
num:=num+1;
end if;
case num is
when 00=>d<="11111111";when 01=>d<="11111110"; when 02=>d<="11111100";
when 03=>d<="11111001";when 04=>d<="11110101"; when 05=>d<="11101111";
when 06=>d<="11101001";when 07=>d<="11100001"; when 08=>d<="11011001";
when 09=>d<="11001111";when 10=>d<="11000101"; when 11=>d<="10111010";
when 12=>d<="10101110";when 13=>d<="10100010"; when 14=>d<="10010110";
when 15=>d<="10001001";when 16=>d<="01111100"; when 17=>d<="01110000";
when 18=>d<="01100011";when 19=>d<="01010111"; when 20=>d<="01001011";
when 21=>d<="01000000";when 22=>d<="00110101"; when 23=>d<="00101011";
when 24=>d<="00100010";when 25=>d<="00011010"; when 26=>d<="00010011";
when 27=>d<="00001101";when 28=>d<="00001000"; when 29=>d<="00000100";
when 30=>d<="00000001";when 31=>d<="00000000"; when 32=>d<="00000000";
when 33=>d<="00000001";when 34=>d<="00000100"; when 35=>d<="00001000";
when 36=>d<="00001101";when 37=>d<="00010011"; when 38=>d<="00011010";
when 39=>d<="00100010";when 40=>d<="00101011"; when 41=>d<="00110101";
when 42=>d<="01000000";when 43=>d<="01001011"; when 44=>d<="01010111";
when 45=>d<="01100011";when 46=>d<="01110000"; when 47=>d<="01111100";
when 48=>d<="10001001";when 49=>d<="10010110"; when 50=>d<="10100010";
when 51=>d<="10101110";when 52=>d<="10111010"; when 53=>d<="11000101";
when 54=>d<="11001111";when 55=>d<="11011001"; when 56=>d<="11100001";
when 57=>d<="11101001";when 58=>d<="11101111"; when 59=>d<="11110101";
when 60=>d<="11111001";when 61=>d<="11111100"; when 62=>d<="11111110";
when 63=>d<="11111111";
when others=>null;
end case;
end if;
end process;
end a;
其中clk 24M，仿真了0.2ms都没反应，求各位帮忙看下是语言的问题还是其他方面的问题~~ 没问题 可能是你仿真错误 网络也需要尊严呀！ 回复【楼主位】henglong9752
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谢谢楼下的，有师兄对我说需要赋初值才行，可是我对vhdl里怎么写testbench跟赋初值都挺生疏……楼下的能赐教么 我也是开始学CPLD不过学的是verilog HDL ，帮你顶一下了。 library ieee;
use ieee.std_logic_1164.all;
use work.sin_gen;
entity TestBenchOfSinGen is
end entity;
architecture Sim Of TestBenchOfSinGen is
component sin_gen
port (clk,clr:in std_logic;
d:out std_logic_vector(7 downto 0));
end component;
signal clk: std_logic:='1';
signal clr: std_logic:='1';
signal d: std_logic_vector(7 downto 0):=(others=>'0');
begin
u1: sin_gen port map(clk,clr,d);
clkGen: process(clk)
begin
clk <= not clk after 10ns;
end process;
end architecture;
没有时间，要出门了，写了一个简单的仿真。调进ModelSim里就可以看到波形了。 actel没有用过
testbench里面初值这样：
initial
begin
... ...
end
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