求助:控制TLV320AIC23（SPI方式）
请问各位大虾，做过FPGA控制音频芯片TLV320AIC23（SPI方式）?小弟我写出来的代码仿真后就是得不到正确的结果。
目的是重复将11个寄存器reg【15：0】内的数据串行依次输出，
我用了2个计数器。cnt：0-16和cnt2：0-11
cnt重复计数，每cnt=16，cnt2计数
在cnt：0-16计数过程中将reg【15：0】内的内容串行输出。
在cnt2计数中重复11个寄存器。
请各位帮忙指点下：
module audio(clkin,cs_spi,sclk,sdin,stop,cnt,cnt2);
input clkin;
output cs_spi;
output sclk;
output sdin;
output stop;
output cnt;
output cnt2;// 输出看看
assign sclk=clkin;
//reg sclk;
reg ssclk;
reg cnt;
reg cnt2;
reg sdin;
reg cs_spi;
reg stop;
regrin_1=16'b0000000111111111;////example
regrin_2=16'b0000000111111111;
regrin_3=16'b0000000111111111;
regrin_4=16'b0000000111111111;
regrin_5=16'b0000000111111111;
regrin_6=16'b0000000111111111;
regrin_7=16'b0000000111111111;
regrin_8=16'b0000000111111111;
regrin_9=16'b0000000111111111;
reg rin_10=16'b0000000111111111;
reg rin_11=16'b0000000111111111;
reg rrin_1,rrin_2,rrin_3,rrin_4,rrin_5,rrin_6,rrin_7,rrin_8,rrin_9,rrin_10,rrin_11;
wire sdo_1,sdo_2,sdo_3,sdo_4,sdo_5,sdo_6,sdo_7,sdo_8,sdo_9,sdo_10,sdo_11;
wire cs_spi1,cs_spi2,cs_spi3,cs_spi4,cs_spi5,cs_spi6,cs_spi7,cs_spi8,cs_spi9,cs_spi10,cs_spi11;
spi myspi1(.clk(clkin),.cs(cs_spi1),.rin(rin_1),.sdo(sdo_1));
spi myspi2(.clk(clkin),.cs(cs_spi2),.rin(rin_2),.sdo(sdo_2));
spi myspi3(.clk(clkin),.cs(cs_spi3),.rin(rin_3),.sdo(sdo_3));
spi myspi4(.clk(clkin),.cs(cs_spi4),.rin(rin_4),.sdo(sdo_4));
spi myspi5(.clk(clkin),.cs(cs_spi5),.rin(rin_5),.sdo(sdo_5));
spi myspi6(.clk(clkin),.cs(cs_spi6),.rin(rin_6),.sdo(sdo_6));
spi myspi7(.clk(clkin),.cs(cs_spi7),.rin(rin_7),.sdo(sdo_7));
spi myspi8(.clk(clkin),.cs(cs_spi8),.rin(rin_8),.sdo(sdo_8));
spi myspi9(.clk(clkin),.cs(cs_spi9),.rin(rin_9),.sdo(sdo_9));
spi myspi10(.clk(clkin),.cs(cs_spi10),.rin(rin_10),.sdo(sdo_10));
spi myspi11(.clk(clkin),.cs(cs_spi11),.rin(rin_11),.sdo(sdo_11));
always@(posedge sclk)
begin
if(cnt==16)
cnt<=0;
else
cnt<=cnt+1;
if(cnt==16)
cnt2<=cnt2+1;
case(cnt2)
0:begin
cs_spi<=cs_spi1;
sdin<=sdo_1;
cnt2<=1;end
1:begin
cs_spi<=cs_spi2;
sdin<=sdo_2;
cnt2<=2;end
2:begin
cs_spi<=cs_spi3;
sdin<=sdo_3;
cnt2<=3;end
3:begin
cs_spi<=cs_spi4;
sdin<=sdo_4;
cnt2<=4;end
4:begin
cs_spi<=cs_spi5;
sdin<=sdo_5;
cnt2<=5;end
5:begin
cs_spi<=cs_spi6;
sdin<=sdo_6;
cnt2<=6;end
6:begin
cs_spi<=cs_spi7;
sdin<=sdo_7;
cnt2<=7;end
7:begin
cs_spi<=cs_spi8;
sdin<=sdo_8;
cnt2<=8;end
8:begin
cs_spi<=cs_spi9;
sdin<=sdo_9;
cnt2<=9;end
9:begin
cs_spi<=cs_spi10;
sdin<=sdo_10;
cnt2<=10;end
10:begin
cs_spi<=cs_spi11;
sdin<=sdo_11;
cnt2<=11;end
11:begin
cs_spi<=0;
sdin<=0;
cnt2<=0;end
default:begin
cs_spi<=0;
sdin<=0;
cnt2<=0;end
endcase
end
endmodule
module spi(clk,cs,rin,sdo);
input clk;
input rin;
output cs;
output sdo;
regcnt;
reg cs;
reg sdo;
always@(negedge clk)
case(cnt)
0:begin
cs<=1;
sdo<=rin;
cnt<=1;end
1:begin
cs<=1;
sdo<=rin;
cnt<=2;end
2:begin
cs<=1;
sdo<=rin;
cnt<=3;end
3:begin
cs<=1;
sdo<=rin;
cnt<=4;end
4:begin
cs<=1;
sdo<=rin;
cnt<=5;end
5:begin
cs<=1;
sdo<=rin;
cnt<=6;end
6:begin
cs<=1;
sdo<=rin;
cnt<=7;end
7:begin
cs<=1;
sdo<=rin;
cnt<=8;end
8:begin
cs<=1;
sdo<=rin;
cnt<=9;end
9:begin
cs<=1;
sdo<=rin;
cnt<=10;end
10:begin
cs<=1;
sdo<=rin;
cnt<=11;end
11:begin
cs<=1;
sdo<=rin;
cnt<=12;end
12:begin
cs<=1;
sdo<=rin;
cnt<=13;end
13:begin
cs<=1;
sdo<=rin;
cnt<=14;end
14:begin
cs<=1;
sdo<=rin;
cnt<=15;end
15:begin
cs<=1;
sdo<=rin;
cnt<=16;end
16:begin
cs<=0;
sdo<=0;
cnt<=0;end
default:begin
cs<=0;
sdo<=0;
cnt<=0;end
endcase
endmodule 老兄 用vhdl啊 看不懂 寄存器配置没问题吧？ 公司有用 TLV320AIC14K。
和你用的芯片基本一样，不过就是 用 I2C来控制寄存器读写的。
为什么不在线调试试试看呢？ 只是在仿真？
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