Verilog代码请教?
我想用按钮控制4个LED灯的亮暗,也就是手动跑马灯,请问一下代码有什么问题,我是初学者,请赐教!module button_led(led_switch,led1,led2,led3,led4
);
input led_switch;
output led1,led2,led3,led4;
reg led1,led2,led3,led4;
reg led_num;
always @ (posedge led_switch)
begin
led_num <= led_num+1;
end
always @ (led_num)
begin
if(led_num==2'd0)
begin
led1 <= 1;
led2 <= 0;
led3 <= 0;
led4 <= 0;
end
else if(led_num==2'd1)
begin
led1 <= 0;
led2 <= 1;
led3 <= 0;
led4 <= 0;
end
else if(led_num==2'd2)
begin
led1 <= 0;
led2 <= 0;
led3 <= 1;
led4 <= 0;
end
else if(led_num==2'd3)
begin
led1 <= 0;
led2 <= 0;
led3 <= 0;
led4 <= 1;
end
else
begin
led1 <= 0;
led2 <= 0;
led3 <= 0;
led4 <= 0;
end
end
endmodule 错误提示:
.
ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found
that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
IOB component <led_switch> is placed at site <PAD366>. The corresponding BUFG
component <led_switch_BUFGP> is placed at site <BUFGMUX_X2Y3>. There is only
a select set of IOBs that can use the fast path to the Clocker buffer, and
they are not being used. You may want to analyze why this problem exists and
correct it. If this sub optimal condition is acceptable for this design, you
may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this
message to a WARNING and allow your design to continue. However, the use of
this override is highly discouraged as it may lead to very poor timing
results. It is recommended that this error condition be corrected in the
design. A list of all the COMP.PINs used in this clock placement rule is
listed below. These examples can be used directly in the .ucf file to
override this clock rule.
< NET "led_switch" CLOCK_DEDICATED_ROUTE = FALSE; >
Phase 4.2Initial Placement for Architecture Specific Features
REAL time: 11 secs
Total REAL time to Placer completion: 11 secs
Total CPUtime to Placer completion: 8 secs
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
Mapping completed.
See MAP report file "button_led_map.mrp" for details.
(Checksum:deecdbc8) Problem encountered during the packing phase.
Design Summary
--------------
Number of errors : 2
Number of warnings : 0
Process "Map" failed 在线等待中。。。。 注意阻塞赋值与非阻塞赋值,组合逻辑与时序逻辑的区别。 LS的高手,能否说清楚一点,菜鸟新手,请指教一下,谢谢! 你这个还得做按键去抖动。。 关键是编译都过不去啊!郁闷,不知道问题出在哪里? 时钟信号不能最优路径,解决办法,在约束文件(.ucf文件)后面加上这一句即可:
NET "led_switch" CLOCK_DEDICATED_ROUTE = FALSE; to roasn 冰封的心,谢谢,加了这句,果然可以了,为什么要这样啊? 楼上不要误导,治标不治本
。这个代码写得一点都不规范,后面的组合逻辑都是非阻塞赋值。
有时间的话,多看看书上的例程。注意时序逻辑和组合逻辑的区别。
不介意的话,也可以看看我那个消抖的帖子。
手机回帖,不周,请原谅。 受教,受教! 回复【9楼】tear086.COM 缺氧
楼上不要误导,治标不治本
。这个代码写得一点都不规范,后面的组合逻辑都是非阻塞赋值。
有时间的话,多看看书上的例程。注意时序逻辑和组合逻辑的区别。
不介意的话,也可以看看我那个消抖的帖子。
手机回帖,不周,请原谅。
-----------------------------------------------------------------------
我没看他的程序,他的代码写得是否规范我没看,我只看了他的Error信息 module button_led(clk,led_switch,led1,led2,led3,led4
);
input clk,led_switch;
output led1,led2,led3,led4;
reg led1,led2,led3,led4;
reg led_num;
reg count;
/*********************进行按键消抖处理*********************/
parametercout = 539999;
reg current_state;
reg last_state;
always @ (posedge clk)
begin
if(count==cout)//满20ms就记录开关状态
begin
count <= 0;
current_state <= led_switch;
end
else
count <= count + 1;
end
always @ (posedge clk)
last_state <= current_state;
always @ (posedge clk)
begin
if(last_state==0 && current_state ==1 )//按下是1,没按下是0
led_num <= led_num+1;
end
always @ (led_num)
begin
if(led_num==2'd0)
begin
led1 = 1;
led2 = 0;
led3 = 0;
led4 = 0;
end
else if(led_num==2'd1)
begin
led1 = 0;
led2 = 1;
led3 = 0;
led4 = 0;
end
else if(led_num==2'd2)
begin
led1 = 0;
led2 = 0;
led3 = 1;
led4 = 0;
end
else if(led_num==2'd3)
begin
led1 = 0;
led2 = 0;
led3 = 0;
led4 = 1;
end
end
endmodule
为什么我加入消抖之后就不用再.UCF中加入那句话呢NET "led_switch" CLOCK_DEDICATED_ROUTE = FALSE; 我再看了你的代码,tear086 .COM 缺氧说得很对,那是你的代码导致的问题。
你没有分清组合逻辑与时序逻辑,阻塞语句与非阻塞语句也分不清,
导致综合器没法为你的代码进行优化的综合,最终导致时钟信号无法最优路径。
12楼的代码不需要那句不是因为加入消抖,而是阻塞语句与非阻塞语句用对了。 TO :冰封的心
我将一楼的程序中按钮led_switch从普通的IO脚变成时钟脚,还是一楼的程序,只是脚位分配的不一样,这时候就可以编译成功了,
为什么? LED1,LED2,LED3,LED4的赋值用阻塞与非阻塞在这里应该没有什么区别才对啊,这四个灯的状态又不互相影响,我这样理解对吗? 实际效果虽然一样,但是对综合器来说就不一样了 好的,那请问:冰封的心
我将一楼的程序中按钮led_switch从普通的IO脚变成时钟脚,还是一楼的程序,只是脚位分配的不一样,这时候就可以编译成功了,
为什么? always @ (posedge led_switch)
begin
led_num <= led_num+1;
end
在以上语句中,led_switch是作为计数器led_num的时钟使用,那么就要求led_switch指定为专用的时钟输入引脚,否则led_switch到芯片内led_num寄存器的路径是普通布线路径而不是专用的全局时钟路径,会导致时钟抖动极大,时序不能保证。 谢谢楼上的解答,感觉挺有道理的! 好帖,帮我解决了问题~~~~顶啊 linxiaolong 发表于 2010-4-6 10:32 static/image/common/back.gif
LED1,LED2,LED3,LED4的赋值用阻塞与非阻塞在这里应该没有什么区别才对啊,这四个灯的状态又不互相影响,我 ...
关于这点,我个人觉得你是对的,他们是错的。 几年之后,看到这个帖子,回获颇丰。
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