新手求助。。4*4矩阵键盘
一个很简单的矩阵键盘程序。。。如下:module key(clk,rst,row,column,dataout,en);
input clk,rst;
input column,row;
output dataout;
output en;
reg en=4'b0000;
//++++++++++++++++++++++++++++++++++++++
// 分频器 开始
//++++++++++++++++++++++++++++++++++++++
reg cnt;
always@(posedge clk,negedge rst)
begin
if(!rst)
begin
duan<=0;
en<=0;
end
else begin
cnt<=cnt+1; 错误行!!!!!!!!!!!!!!!!!!!!!!!!!!!
end
end
//++++++++++++++++++++++++++++++++++++++
// 扫描 开始
//++++++++++++++++++++++++++++++++++++++
reg duan;
always@(cnt)
begin
case(row)
4'b 1110:
case(column)
4'b1110: duan<=0;
4'b1101: duan<=1;
4'b1011: duan<=2;
4'b0111: duan<=3;
default: duan<=0;
endcase
4'b 1101:
case(column)
4'b1110: duan<=4;
4'b1101: duan<=5;
4'b1011: duan<=6;
4'b0111: duan<=7;
default: duan<=0;
endcase
4'b 1011:
case(column)
4'b1110: duan<=8;
4'b1101: duan<=9;
4'b1011: duan<=10;
4'b0111: duan<=11;
default: duan<=0;
endcase
4'b 0111:
case(column)
4'b1110: duan<=12;
4'b1101: duan<=13;
4'b1011: duan<=14;
4'b0111: duan<=15;
default: duan<=0;
endcase
default: duan<=0;
endcase
end
//++++++++++++++++++++++++++++++++++++++
// 输出开始
//++++++++++++++++++++++++++++++++++++++
reg dataout;
always@(duan)
begin
case(duan)
4'd0 :dataout<=8'h3f;
4'd1 :dataout<=8'h60;
4'd2 :dataout<=8'h5b;
4'd3 :dataout<=8'h4f;
4'd4 :dataout<=8'h66;
4'd5 :dataout<=8'h6d;
4'd6 :dataout<=8'hd6;
4'd7 :dataout<=8'h7;
4'd8 :dataout<=8'h7f;
4'd9 :dataout<=8'h6f;
4'd10 :dataout<=8'h77;
4'd11 :dataout<=8'h7c;
4'd12 :dataout<=8'h39;
4'd13 :dataout<=8'h5e;
4'd14 :dataout<=8'h79;
4'd15 :dataout<=8'h71;
default: dataout<=8'h3f;
endcase
end
endmodule Error (10048): Verilog HDL error at key.v(21): values cannot be assigned directly to all or part of array "cnt" - assignments must be made to individual elements only
Error (10044): Verilog HDL error at key.v(21): expression cannot reference entire array "cnt" 呵呵。
不介意的话,可以参考一下我写的代码。
http://www.ourdev.cn/bbs/bbs_content.jsp?bbs_sn=3886510 呵呵,看过您写的代码,想仔细先搞个简单的,练练手,一步一步再弄个想您那样的。。。我这个没考虑防抖 可以把错误,用文字贴出来吗。我手机看不清楚,不好意思。 回复【4楼】tear086 .COM 缺氧
-----------------------------------------------------------------------
谢谢您的不吝赐教:
Error (10048): Verilog HDL error at key.v(21): values cannot be assigned directly to all or part of array "cnt" - assignments must be made to individual elements only
Error (10044): Verilog HDL error at key.v(21): expression cannot reference entire array "cnt" cnt加个复位初值就可以了,加在(!rst_n)后面的begin-end块内。 回复【6楼】tear086 .COM 缺氧
-----------------------------------------------------------------------
加了之后变成了:
//++++++++++++++++++++++++++++++++++++++
// 分频器 开始
//++++++++++++++++++++++++++++++++++++++
reg cnt;
always@(posedge clk,negedge rst)
begin
if(!rst)
begin
duan<=0;
en<=0;
cnt<=0;
end
else begin
cnt<=cnt+1;
end
end
但是综合后,又多出来个错误,Error (10048): Verilog HDL error at key.v(19): values cannot be assigned directly to all or part of array "cnt" - assignments must be made to individual elements only,错误指向刚才增加的那行 刚才发现cnt定义反了,应该把放在前面,我真太粗心了。。。综合之后还是有错,继续修改 module key(clk,rst,row,column,dataout,en);
input clk,rst;
input column,row;
output dataout;
output en;
reg en=4'b0000;
//++++++++++++++++++++++++++++++++++++++
// 分频器 开始
//++++++++++++++++++++++++++++++++++++++
reg cnt;
always@(posedge clk,negedge rst)
begin
if(!rst)
begin
duan<=0;
en<=0;
end
else begin
cnt<=cnt+1;
end
end
//++++++++++++++++++++++++++++++++++++++
// 扫描 开始
//++++++++++++++++++++++++++++++++++++++
wire cnt_flag=cnt;
reg duan;//!!!!!!!!错?0028!!!!!!!/////
always@(cnt_flag)//!!!!!!错误10029!!!!!!!!/////
begin
case(row)
4'b 1110:
case(column)
4'b1110: duan<=0;
4'b1101: duan<=1;
4'b1011: duan<=2;
4'b0111: duan<=3;
default: duan<=0;
endcase
4'b 1101:
case(column)
4'b1110: duan<=4;
4'b1101: duan<=5;
4'b1011: duan<=6;
4'b0111: duan<=7;
default: duan<=0;
endcase
4'b 1011:
case(column)
4'b1110: duan<=8;
4'b1101: duan<=9;
4'b1011: duan<=10;
4'b0111: duan<=11;
default: duan<=0;
endcase
4'b 0111:
case(column)
4'b1110: duan<=12;
4'b1101: duan<=13;
4'b1011: duan<=14;
4'b0111: duan<=15;
default: duan<=0;
endcase
default: duan<=0;
endcase
end
//++++++++++++++++++++++++++++++++++++++
// 输出开始
//++++++++++++++++++++++++++++++++++++++
reg dataout;
always@(duan)
begin
case(duan)
4'd0 :dataout<=8'h3f;
4'd1 :dataout<=8'h60;
4'd2 :dataout<=8'h5b;
4'd3 :dataout<=8'h4f;
4'd4 :dataout<=8'h66;
4'd5 :dataout<=8'h6d;
4'd6 :dataout<=8'hd6;
4'd7 :dataout<=8'h7;
4'd8 :dataout<=8'h7f;
4'd9 :dataout<=8'h6f;
4'd10 :dataout<=8'h77;
4'd11 :dataout<=8'h7c;
4'd12 :dataout<=8'h39;
4'd13 :dataout<=8'h5e;
4'd14 :dataout<=8'h79;
4'd15 :dataout<=8'h71;
default: dataout<=8'h3f;
endcase
end
endmodule
错误提示:Error (10028): Can't resolve multiple constant drivers for net "duan.1111" at key.v(29)
Error (10029): Constant driver at key.v(30)
Error: Can't elaborate top-level user hierarchy 手机看帖,回帖。不周,请包涵。
always@(cnt_flag)块是时序逻辑,要加边沿修饰符:posedge或negedge。后面的always@(duan)块,最好用always@(*),是组合逻辑,用阻塞赋值:=。 谢谢,又学到东西了,但是按上述改完之后:
module key(clk,rst,row,column,dataout,en);
input clk,rst;
input column,row;
output dataout;
output en;
reg en=4'b0000;
//++++++++++++++++++++++++++++++++++++++
// 分频器 开始
//++++++++++++++++++++++++++++++++++++++
reg cnt;
always@(posedge clk,negedge rst)
begin
if(!rst)
begin
duan<=0;
en<=0;
end
else begin
cnt<=cnt+1;
end
end
//++++++++++++++++++++++++++++++++++++++
// 扫描 开始
//++++++++++++++++++++++++++++++++++++++
wire cnt_flag=cnt;
reg duan;//!!!!!!!!!!!!!!!!!错误10028
always@(posedge cnt_flag)
begin
case(row)
4'b 1110:
case(column)
4'b1110: duan=0;
4'b1101: duan=1;
4'b1011: duan=2;
4'b0111: duan=3;
default: duan=0;
endcase
4'b 1101:
case(column)
4'b1110: duan=4;
4'b1101: duan=5;
4'b1011: duan=6;
4'b0111: duan=7;
default: duan=0;
endcase
4'b 1011:
case(column)
4'b1110: duan=8;
4'b1101: duan=9;
4'b1011: duan=10;
4'b0111: duan=11;
default: duan=0;
endcase
4'b 0111:
case(column)
4'b1110: duan=12;
4'b1101: duan=13;
4'b1011: duan=14;
4'b0111: duan=15;
default: duan=0;
endcase
default: duan=0;
endcase
end//!!!!!!!!!!!!!!!!!!!!!错误10029
//++++++++++++++++++++++++++++++++++++++
// 输出开始
//++++++++++++++++++++++++++++++++++++++
reg dataout;
always@(*)
begin
case(duan)
4'd0 :dataout=8'h3f;
4'd1 :dataout=8'h60;
4'd2 :dataout=8'h5b;
4'd3 :dataout=8'h4f;
4'd4 :dataout=8'h66;
4'd5 :dataout=8'h6d;
4'd6 :dataout=8'hd6;
4'd7 :dataout=8'h7;
4'd8 :dataout=8'h7f;
4'd9 :dataout=8'h6f;
4'd10 :dataout=8'h77;
4'd11 :dataout=8'h7c;
4'd12 :dataout=8'h39;
4'd13 :dataout=8'h5e;
4'd14 :dataout=8'h79;
4'd15 :dataout=8'h71;
default: dataout=8'h3f;
endcase
end
endmodule
Error (10028): Can't resolve multiple constant drivers for net "duan.1111" at key.v(29)
Error (10029): Constant driver at key.v(68)
Error: Can't elaborate top-level user hierarchy 回复【10楼】tear086 .COM 缺氧
-----------------------------------------------------------------------
您真是太客气了。。。谢谢您。。。。郁闷啊。。。程序还是不好用
页:
[1]