mcu总线到WishBone的转接
MCU总线到FPGA内部总线的转接欢迎讨论
wbm16_cyc_o,
wbm16_stb_o,
wbm16_ack_i,
信号处理是否正确？
/**
*/
module par16_bridge(
wb_clk_i,
wb_rst_i,
// MCU Bus Signals
mcu_adr_pad,
mcu_dat_pad,
mcu_xrd_pad,
mcu_xwe_pad,
mcu_xrw_pad,
mcu_xcs_pad,
// Wishbone Master Signals
wbm16_adr_o,
wbm16_dat_o,
wbm16_dat_i,
wbm16_cyc_o,
wbm16_stb_o,
wbm16_we_o,
wbm16_ack_i,
wbm16_sel_o
);
input wb_clk_i, wb_rst_i;
input mcu_adr_pad;
inout mcu_dat_pad;
input mcu_xrd_pad, mcu_xwe_pad;
input mcu_xrw_pad, mcu_xcs_pad;
output wbm16_adr_o;
output wbm16_sel_o;
input wbm16_dat_i;
output wbm16_dat_o;
output wbm16_cyc_o, wbm16_stb_o, wbm16_we_o;
input wbm16_ack_i;
reg datlatch;
reg wb16_ack_o, wbm16_cyc_o, wbm16_stb_o;
/**********************************************************************************/
assign wbm16_adr_o = mcu_adr_pad;
assign wbm16_sel_o = 4'b1111;
assign wbm16_we_o = !mcu_xrw_pad;
assign wbm16_cyc_o = !mcu_xcs_pad;
assign wbm16_stb_o = !mcu_xcs_pad;
always @(posedge wb_clk_i) begin
if (!mcu_xcs_pad && !mcu_xrd_pad) begin
wbm16_dat_o <= mcu_dat_pad;
epwbm_stb_o <= 1'b1;
end
if (!mcu_xcs_pad && !mcu_xwe_pad)
mcu_dat_pad <= wbm16_dat_i;
else
mcu_dat_pad <= 16'hzzzz;
if (!mcu_xcs_pad && wbm16_ack_i)
epwbm_stb_o <= 1'b0;
end
end
/**********************************************************************************/
/**********************************************************************************/
endmodule 回复【楼主位】sllsky
-----------------------------------------------------------------------
mark
楼主高义，何不搞个Avalon总线和Wishbone总线的互联演示小册子。 这么冷清啊，欢迎讨论啊 代码有问题吧？
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