SYNPLIFY综合失败,各位大哥帮小弟看下问题在哪呀?
SYNPLIF报错“ CL123 The logic for Q_reg does not match a standard flip-flop NOP0911260.v (630)”下面是V代码:谢谢
module DFC_120_120(CDN, CPN, CPP, D, Q);
input CDN;
input CPN;
input CPP;
input D;
output Q;
reg Q_reg;
always @(posedge CPP or negedge CPN or negedge CDN) begin
if (!CDN) begin
Q_reg <= 1'b0;
end
else begin
Q_reg <= D;
end
end
assign #1 Q = Q_reg;
endmodule// DFC_120_120
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