等精度测频
以下是一种等精度测频的代码，可以使用。module mesureFreq (fx,fbase,fgate,comp,rclk,load,fbaseout,fxout);
input fx;
input fbase;
input fgate;
input rclk;
input load;
output comp;
output fbaseout;
output fxout;
reg startCnt;
reg comp;
reg fbaseCntTemp,fxCntTemp;
reg fbaseCnt,fxCnt;
reg count;
reg fbaseout_buf,fxout_buf;
/*-------测频部分------*/
always @ (posedge fbase)
begin
if(startCnt)
begin
fbaseCntTemp <= fbaseCntTemp + 1'b1; //* base count
end
else
begin
fbaseCntTemp <= 32'h00000000;
end
end
always @ (posedge fx)
begin
if(startCnt)
fxCntTemp <= fxCntTemp + 1'b1; //* fx count
else
fxCntTemp <= 32'h00000000;
end
//synchronous fgate
always @ (posedge fx)
begin
if(fgate)
begin
startCnt <= 1'b1;
comp <= 1'b0;
end
else
begin
startCnt <= 1'b0;
comp <= 1'b1;
end
end
always @ (negedge startCnt)
begin
fxCnt <= fxCntTemp;
fbaseCnt <= fbaseCntTemp;
end
/*-------数据传输部分------*/
always @ (posedge rclk)
begin
if(load)
begin
count <= 0;
end
else
begin
fbaseout_buf <= fbaseCnt;
fxout_buf <= fxCnt;
count <= count+1'b1;
end
end
assign fbaseout = fbaseout_buf;
assign fxout = fxout_buf;
endmodule
我用的是EPM570，在实际使用中发现测频不是很稳定，跳动比较厉害，有时还会出现极大值和极小值，但是如果我测CPLD分频出来的时钟是很稳的，不知道是不是没有做时序约束的原因，在综合的时候有以下警告：
1、Warning: Found pins functioning as undefined clocks and/or memory enables
2、Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
3、Warning: Circuit may not operate. Detected 32 non-operational path(s) clocked by clock "fx" with clock skew larger than data delay. See Compilation Report for details.
请问各位大虾，能否给点建议改进一下，谢谢~！ 我也要做这个最近 可是我用的是vhdl....帮顶了 mark mark 信号调整电路产生的干扰和信号自身的噪声影响不容忽视！ mark mark mark
{:shocked:} 没有注释,看的好艰难
xiaohe669 发表于 2011-8-4 17:46
信号调整电路产生的干扰和信号自身的噪声影响不容忽视！
能不能传授点经验？谢谢! 输入管脚设置成施密特类型没有？ oped001 发表于 2013-5-16 07:31 static/image/common/back.gif
能不能传授点经验？谢谢!
加个斯密特触发器就行
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