bestwyysx 发表于 2009-12-14 18:26:09

请教一个FPGA接51单片机数据的问题

我写了一个PWM发生程序,需要单片机给FPGA发送占空比,可是怎么也不对,用的是51单片机的P0,P2口
PWM 的verilog 代码:
`define pwm_width_addr16'hff00
`define pwm_period_addr 16'hff01
`define no_rw 2'h0
`define rw_pwmwidth2'h1
`define rw_pwmperiod 2'h2
module pwm(mcu_ad,mcu_a,ale,wr,rd,pwm,clk);
inout mcu_ad;
input mcu_a;
input ale;
input wr;
input rd;
output pwm;
input clk;
reg mcu_ad_reg;
reg pwm_reg;
reg count;
reg width_count;
reg period_count;
reg addr_sel;

initial
begin
   period_count=8'b11111111;
   width_count=8'b00000000;
end
always @ (negedge ale)
begin
if({mcu_a,mcu_ad}== `pwm_width_addr)
begin
   addr_sel = `rw_pwmwidth;
end
else if({mcu_a,mcu_ad}==`pwm_period_addr)
begin
   addr_sel=`rw_pwmperiod;
end
else
   addr_sel= `no_rw;
end
always @ (posedge wr)
begin
if(addr_sel== `rw_pwmwidth)
width_count = mcu_ad;
else if(addr_sel==`rw_pwmperiod)
period_count = mcu_ad;
end
always @(negedge rd)
begin
if(addr_sel== `rw_pwmwidth)
mcu_ad_reg=width_count;
else if (addr_sel==`rw_pwmperiod)
mcu_ad_reg=period_count;
end
always @ (posedge clk)
begin
if(count>=period_count-1)
count<=0;
else
count<=count+1;
end
always @ (posedge clk)
begin
if(count<width_count)
pwm_reg=6'b111111;
else
pwm_reg=6'b000000;
end
assign mcu_ad=((rd==1'b1)||(addr_sel==`no_rw))?8'hz:mcu_ad_reg;
assign pwm=pwm_reg;
endmodule


C51 代码:
#include"reg51.h"
#include"address.h"
#include"intrins.h"

#define uint unsigned int
#define uchar unsigned char


void wr_pwm(unsigned int ADDR, unsigned char DATA)
{
*((unsigned char xdata *)ADDR)=DATA;
}

unsigned char rd_pwm(unsigned int ADDR)
{
return   *((unsigned char xdata *)ADDR);
}

void delay_10us(uchar n)
{
   do
   {
   _nop_();
   _nop_();
   _nop_();
   _nop_();
   _nop_();
   }while(--n);
}

void delay_ms(uint n)
{
do
{
    delay_10us(131);
   }while(--n);
}


void main()
{
wr_pwm(pwm_period_addr,0xff);
wr_pwm(pwm_width_addr,0x00);
delay_ms(10);
while        (1)
{
   pwm_width=pwm_width+1;
   wr_pwm(pwm_width_addr,pwm_width);
   if(pwm_width==0xff)
    pwm_width=0;
   delay_ms(100);
}
}

请高手指点一下,谢谢,

ngzhang 发表于 2009-12-15 02:18:29

粗看了一下你的verilog部分代码,使用了大量的latch,这个用fpga实现可能会有一些未知的结果。另外initial是不能综合的,信号要复位。既然功能不是太复杂,能否改成时序逻辑电路,另外做一下仿真看看结果?

bestwyysx 发表于 2009-12-15 08:48:33

你好,能具体指点一下吗?
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