请大家帮我看下这个状态机
http://cache.amobbs.com/bbs_upload782111/files_23/ourdev_512095.JPG(原文件名:1.JPG)
module s1 (clk,rst_n,light);
input clk;
input rst_n;
output light;
parameter s0=4'b0000,
s1=4'b0001,
s2=4'b0010,
s22=4'b0011,
s3=4'b0011,
s33=4'b0100,
s4=4'b0100,
s44=4'b0101;
reg cnt;
reg light_temp;
assign light=light_temp;
reg state,next_state;
always @ (posedge clk)
if(!rst_n)
state<=s0;
else
state<=next_state;
always @ (state)
case(state)
s0:begin
light_temp=8'b0000_0001;
end
s1:begin
light_temp<={light_temp,light_temp};
end
s2:begin
light_temp<=8'b1000_0000;
end
s22:begin
light_temp<={light_temp,light_temp};
end
s3:begin
light_temp<=8'b0001_1000;
end
s33:begin
light_temp<={light_temp,light_temp};
light_temp<={light_temp,light_temp};
end
s4:begin
light_temp<=8'b1000_0001;
end
s44:begin
light_temp<={light_temp,light_temp};
light_temp<={light_temp,light_temp};
end
default:light_temp<=light_temp;
endcase
always @ (state or cnt)
case(state)
s0:next_state<=s1;
s1:
begin
if(cnt==7)
begin
next_state<=s2;
cnt<=0;
end
else
begin
next_state<=s1;
cnt<=cnt+1;
end
end
s2:
begin
next_state<=s22;
end
s22:begin
if(cnt==7)
begin
next_state<=s3;
cnt<=0;
end
else
begin
next_state<=s22;
cnt<=cnt+1;
end
end
s3:begin
next_state<=s33;
end
s33:begin
if(cnt==3)
begin
next_state<=s4;
cnt<=0;
end
else
begin
next_state<=s33;
cnt<=cnt+1;
end
end
s4:
begin
next_state<=s44;
end
s44:begin
if(cnt==3)
begin
next_state<=s1;
cnt<=0;
end
else
begin
next_state<=s44;
cnt<=cnt+1;
end
end
default:next_state<=s1;
endcase
endmodule 为什么会出现孤立的状态 我知道了。。。。。粗心，前面的状态分配有问题
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