新手 找大侠救命
下面是我写的状态机 就是编译成功后没那个状态机的效果希望个位大侠帮帮我这个新手。。
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
--use ieee.std_logic_signed.all;
entity jia1 is
port( clk,res,up,dow: in std_logic;
-- uu : in std_logic_vector(1 downto 0);
d : outbit_vector(1 downto 0);
res1,up1,down1: out std_logic
);
end;
architecture a of jia1 is
type state_type is (s0,s1,s2,s3);
signal old_state,new_state : state_type :=s0;
begin
process(clk,res)
begin
if res='1' then
-- new_state <= s0;
res1 <= '1';
elsif clk'event and clk='1'then
new_state<=old_state;
end if;
end process;
process(new_state, up ,dow)
begin
case new_state is
when s0=>
if up='0' then
old_state<=s1;
up1 <= '1';
down1 <= '0';
elsif dow='0' then
up1 <= '0';
old_state <=s3;
down1 <= '1';
end if;
d <="00";
when s1=>
if up='0' then
old_state<=s2;
up1 <= '1';
down1 <= '0';
elsif dow='0' then
up1 <= '0';
old_state <=s0;
down1 <= '1';
end if;
d <="01";
when s2=>
if up='0' then
old_state<=s3;
up1 <= '1';
down1 <= '0';
elsif dow='0' then
up1 <= '0';
old_state <=s1;
down1 <= '1';
end if;
d <="10";
when s3=>
if up='0' then
old_state<=s0;
up1 <= '1';
down1 <= '0';
elsif dow='0' then
up1 <= '0';
down1 <= '1';
old_state <=s2;
end if;
d <="11";
end case;
end process;
end; 看了你写的程序，你的输出up1,down1: out std_logic 只与输入up,dow: in std_logic;有关与状态无关。不应写在状态机里的
if--elseif--end if 里面。
还有输出res1: out std_logic 的值不明确。
我猜你的思路应该要用一个米里型状态机来完成。
参考如下：不知道是不是和你的思路一样。
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
--use ieee.std_logic_signed.all;
entity skd020 is
port( clk,res,up,dow: in std_logic;
d: outbit_vector(1 downto 0);
res1,up1,down1: out std_logic);
end skd020;
architecture a of skd020 is
type state_type is (s0,s1,s2,s3);
signal old_state : state_type :=s0;
begin
process(clk)
begin
if res='1' then
old_state<=s0;
res1<='1';
elsif clk'event and clk='1'then
res1<='0';
case old_state is
when s0=>
if up='0' then
old_state<=s1;
elsif dow='0' then
old_state <=s3;
end if;
when s1=>
if up='0' then
old_state<=s2;
elsif dow='0' then
old_state <=s0;
end if;
when s2=>
if up='0' then
old_state<=s3;
elsif dow='0' then
old_state <=s1;
end if;
when s3=>
if up='0' then
old_state<=s0;
elsif dow='0' then
old_state <=s2;
end if;
end case;
end if;
end process;
process(up,dow,old_state,clk)
begin
if clk'event and clk='1' then
case old_state is
when s0=>
d <="00";
if up='0' then
up1<='1';
down1<='0';
elsif dow='0' then
up1<='0';
down1<='1';
end if;
when s1=>
d <="01";
if up='0' then
up1<='1';
down1<='0';
elsif dow='0' then
up1<='0';
down1<='1';
end if;
when s2=>
d <="10";
if up='0' then
up1<='1';
down1<='0';
elsif dow='0' then
up1<='0';
down1<='1';
end if;
when s3=>
d <="11";
if up='0' then
up1<='1';
down1<='0';
elsif dow='0' then
up1<='0';
down1<='1';
end if;
end case;
end if;
end process;
end;
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