我的这段锁存器代码为什么出现警告
我的这段代码为什么出现警告module LATCH4(CLRB,CLK,D,Q);
input CLK,CLRB;
input D;
output Q;
reg Q;
always @(CLK or CLRB)
begin
if(!CLRB) Q<=0;
else Q<=D;
end
endmodule
Warning (10235): Verilog HDL Always Construct warning at LATCH4.v(9): variable "D" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Design contains 1 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "CLK" 你的引脚映射对了么，
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