VHDL在maxplus2中编译时出错，请高手指点！！！
原代码（书里抄的，经反复校对没有打错）如下：library ieee;
use ieee.std_logic_1164.all;
-------------------------------------
package my_package is
function positive_edge(signal s: std_logic)
return boolean;
end my_package;
----------------------------------------
package body my_package is
function positive_edge(signal s: std_logic)
return boolean is
begin
return s'event and s = '1';
end positive_edge;
end my_package;
-----------------------------------------
-------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.my_package.all;
----------------------------
entity dff2 is
port (d, clk, rst: in std_logic;
q: out std_logic);
end dff2;
-------------------------------
architecture my_arch of dff2 is
begin
process (clk, rst)
begin
if (rst = '1') then q <= '0' ;
elsif positive_edge(clk) then q <= d;
end if;
end process;
end my_arch;
http://cache.amobbs.com/bbs_upload782111/files_16/ourdev_462320.jpg
(原文件名:%E6%88%AA%E5%9B%BE1.jpg)
编译时出错，不知道错误原因，应该怎么修改？
谢谢大家！！！ Line 31 是哪行？ 29 process (clk, rst)
30 begin
31 if (rst = '1') then q <= '0' ;
32 elsif positive_edge(clk) then q <= d;
33 end if;
34 end process; Xilinx ISE语法检查可以通过 process (clk, rst)
begin
if (rst = '1') then
q <= '0' ;
else
if rising_edge(clk) then
q <= d;
end if;
end if;
end process;
这样写看看 干嘛不用 Quartus II 呢，可以通过啊 maxplus2这个古董对vhdl和verilog支持都不全，很多编不过的，建议楼主听从楼上的建议，不要用这个了，换Quartus II。
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