请教一个用CPLD做接口电路的问题!
我现在用单片机和CPLD以总线的方式连接,我的想法是,数据总线传输数据,然后到CPLD里面处理,处理后以不同的通讯方式传输出去,如:UART.IIC,SPI等方式!
但是我把所有的IO分组,每组4个IO口,这4个IO口可以用来做UART,SPI,IIC和4个IO口,这个可以通过2根控制总线来选择!
我所有组的通讯方式可以变化,也就是说,如果我这个组的想做UART,我下个时刻我想做IIC,
我现在用的VHDL语言来实现,但是我如果用case语句来做的话,总是提示有警告!不知道怎么解决!我贴出代码!希望能帮我解决下!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MODULE is
------------------------------------------
port (
MODULE_RST: instd_logic;
MODULE_ADDRIN: instd_logic_vector( 1 downto 0 );
MODULE_OUT: outstd_logic_vector( 3 downto 0 );
MODULE_IN: instd_logic_vector( 3 downto 0 )
);
------------------------------------------
end MODULE;
architecture Behavioral of MODULE is
------------------------------------------
component BUFGP
port ( I: in std_logic; O: out std_logic );
end component;
------------------------------------------
------------------------------------------
signal MoudleOUT: std_logic;
signal MoudleIN: std_logic;
------------------------------------------
begin
MODULE_ADDR_SEL:
process ( MODULE_RST,MODULE_ADDRIN )
begin
if ( MODULE_RST = '0' ) then
case MODULE_ADDRIN is
when "00" =>
MoudleIN <= MODULE_IN(0);
MODULE_OUT(0) <= MoudleOUT ;
when "01" =>
MoudleIN <= MODULE_IN(1);
MODULE_OUT(1) <= MoudleOUT ;
when "10" =>
MoudleIN <= MODULE_IN(2);
MODULE_OUT(2) <= MoudleOUT ;
when "11" =>
MoudleIN <= MODULE_IN(3);
MODULE_OUT(3) <= MoudleOUT ;
when others =>
null;
end case;
end if;
end process MODULE_ADDR_SEL;
end Behavioral;
但是总是有警告,大概意思就是说有latch什么的!
WARNING:Xst:819 - "G:/MG/MGLM/code/CPLD/PJ092703T/src/MODULE.vhd" line 53: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
WARNING:Xst:653 - Signal <MoudleOUT> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:646 - Signal <MoudleIN> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:737 - Found 1-bit latch for signal <MODULE_OUT_0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <MODULE_OUT_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <MODULE_OUT_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <MODULE_OUT_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <MODULE_OUT_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <MODULE_OUT_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <MODULE_OUT_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <MODULE_OUT_3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <MODULE_OUT_3> (without init value) has a constant value of 0 in block <MODULE>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <MODULE_OUT_2> (without init value) has a constant value of 0 in block <MODULE>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <MODULE_OUT_1> (without init value) has a constant value of 0 in block <MODULE>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <MODULE_OUT_0> (without init value) has a constant value of 0 in block <MODULE>. This FF/Latch will be trimmed during the optimization process.
WARNING:Cpld:1006 - Design 'MODULE' has no inputs.
WARNING:Cpld:997 - Error during loading TIMESPEC AUTO_TS_F2F =
WARNING:Cpld:310 - Cannot apply TIMESPEC AUTO_TS_P2P =
WARNING:Cpld:997 - Error during loading TIMESPEC AUTO_TS_P2F =
WARNING:Cpld:310 - Cannot apply TIMESPEC AUTO_TS_F2P =
希望能帮我解决下! latch的提示好像是你在一个case里面只是对一位进行改变而没对其他位如何处理给出说明,所以其他位就保持原状态,即相当于锁存了。如果你在case里面加入对所有其他位的赋值,比如others<=last_value就不会提示这个警告了
这个警告没什么关系的吧。。。
我初学,个人体会,望高手指正 WARNING:Xst:819 - "G:/MG/MGLM/code/CPLD/PJ092703T/src/MODULE.vhd" line 53: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
这个警告不是很明显的吗,敏感信号没有写到敏感列表里面
楼主写的HDL像写的C语言。建议新手把C语言忘了再来学习CPLD吧。 哦!谢谢了1呵呵!我也觉得!
WARNING:Xst:737 - Found 1-bit latch for signal <MODULE_OUT_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <MODULE_OUT_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <MODULE_OUT_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
这个警告有点烦人!
呵呵!我还是先从基本的数字电路开始吧!这个硬件不是软件,有的时候软件算法没问题,但是硬件会有问题的1呵呵!谢谢指教!
页:
[1]