语法错误,谢谢!
always @(state orX)begin
case (state)
S0: if(X)
next_state =S1;
else
next_state =S0;
S1: begin //delay some positive edges of clock
repeat(`Y2RDELAY) @(posedge clock) ;
next_state =S2;
end
S2: begin //delay some positive edges of clock
repeat(`R2GDELAY) @(posedge clock)
next_state =S3;
end
S3: if( X)
next_state =S3;
else
next_state =S4;
S4: begin //delay some positive edges of clock
repeat(`Y2RDELAY) @(posedge clock) ;
next_state =S0;
end
default: next_state =S0;
endcase
end 代码是摘自夏老师翻译的VERILOG HDL数字设计与综合(第二版),我用的是XILINX软件,合成时候语法错误;但MODELSIM可以仿真.
语法错误:Unsupported Event Control Statement: repeat(`Y2RDELAY) @(posedge clock)
谢谢! repeat(`Y2RDELAY) @(posedge clock)
这个是仿真的时候用的,综合不了的。。。 谢谢,如果想综合该怎么写呢? 你心中要有硬件
HDL 描述的是硬件,而不是算法 谢谢,代码本来的意思是 延迟后切换到另外状态,请问这个延迟怎么实现呢? 用计数器吗? 恩 是的可以用计数器延时啊 用计时器延时依然不好写?总感觉别扭:
always @(state orX) 这里面并没有时钟信号,该怎么写呢,想不出来.
如果改成always @(state orX or posedge clk)硬件也没办法综合.
只能这样写:
always @(posedge clk)
begin
case (state)
S0: if(X)
next_state =S1;
else
next_state =S0;
S1: begin //delay some positive edges of clock
repeat(`Y2RDELAY) @(posedge clock) ;
next_state =S2;
end
end always @(posedge clk)
begin
case (state)
S0: if(X)
next_state =S1;
else
begin
next_state =S0;
cnt<=0;
end
S1: begin //delay some positive edges of clock
if (cnt==10)
begin
next_state =S2;
cnt<=0;
end
else
cnt<=cnt+1;
end
end
这样写对吗,很别扭?谢谢
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