请高手给看看这些程序
请高手给看看这些程序 给注释下触发器一 COMPONENT dff1：设计有置位端pset，没有清零端clr
LIBRARY IEEE;
USE IEEE STD_LOGIC_1164.ALL;
ENTITY dff1 IS
PORT(clk,d,pset:IN STD_LOGIC;
q1,q2:OUT STD_LOGIC);
END dff1;
ARCHITECTURE rtl OF dff1 IS
BEGIN
PROCESS(clk,pset)
BEGIN
IF(pset ='0')THEN
q1<='1';
q2<='0';
ELSIF (clk='0' AND clk='1')THEN
q1<=d;
q2<=NOT d;
END IF;
END PROCESS;
END rtl;
触发器二 COMPONENT dff2：设计有清零端clr，没有置位端pset
LIBRARY IEEE;
USE IEEE STD_LOGIC_1164.ALL;
ENTITY dff2 IS
PORT(clk,d,reset:IN STD_LOGIC;
q1,q2:OUT STD_LOGIC);
END dff2;
ARCHITECTURE rtl OF dff2 IS
BEGIN
PROCESS(clk,reset)
BEGIN
IF(pset ='0')THEN
q1<='0';
q2<='1';
ELSIF (clk='0' AND clk='1')THEN
q1<=d;
q2<=NOT d;
END IF;
END PROCESS;
END rtl;
八循环移位寄存器：
LIBRARY IEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITY shift IS
PORT (clk,reset:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR (4 DOWNTO 0));
END shift;
ARCHITECTUREgen_shift OF shift IS
COMPONENT dff1
PORT (d,clk,pset:IN STD_LOGIC;
q0:OUT STD_LOGIC);
END COMPONENT;
COMPONENT dff2
PORT (d,clk,clr:IN STD_LOGIC;
q0:OUT STD_LOGIC);
END COMPONENT;
SIGNALz:STD_LOGIC_VECTOR (4 DOWNTO 0);
BEGIN
u1:dff1 PORT MAP (z(4),clk,reset,z(0));
go: FOR i IN 0 TO 3 GENERATE
u2:dff2PORT MAP (z(i),clk,reset,z(i+1));
END GENERATE;
g1:FOR j IN 0 TO 4 GENERATE
Q(j)<=z(j);
END GENERATE;
END gen_shift; 这不就是用VHDL语言编的代码嘛 去你第一次发帖的看看
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