quartusII 8.0功能仿真出现这个问题是什么原因啊?【恢复】
verilog文件编译过了,功能仿真列表添加也没错误,警告.可点"Start"仿真到99%出现如下错误:
Error: Verific analyzer is not successful with include file
Error: Verific analyzer is not successful with file E:/FPGA_Files/q2/mpu_wr_tb_v10.v
Error: HDC Compilation Failed!!! Detected 6 errors
Error: Quartus II Simulator was unsuccessful. 3 errors, 0 warnings
*.v文件在source目录下和q2工程目录下都如此
望大侠指点... 找到问题了,原来是仿真测试程序中使用了while.改了可以了 楼主我也遇到同样的问题,可是我没用while
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