学习CPLD两个星期了,交个CPLD读PS2键盘的作业~~~
已经下载到芯片里面用键盘验证过了,可以读出键值,不过由于没有加入校验,大概会有4%几率误码,这几天再补补~~哈哈~~由于是刚学,程序有什么不规范的话麻烦各位大虾提醒啊~~THS~~~
module PS2(data,clock,led,clk,num,cat);
input data;
input clock;
input clk;
output led;
output num;
output cat;
wire data; //PS2数据端
wire clock; //PS2时钟端
wire clk;
reg led; //用于二极管显示
reg num; //用于数码管显示
reg cat; //数码管位选
reg data_ram;
reg start; //开始读取键码标志位
reg count; //计数读取的键码
reg i; //循环计数用
reg odd; //奇偶校验标志
reg num_high; //数码管显示高位
reg num_low; //数码管显示低位
initial
begin
led=0;
data_ram=0;
start=0;
count=11;
i=0;
num_high=0;
num_low=0;
num=0;
cat=0;
end
always@(negedge clock)
begin
if(data==0)
start=1;
else
start=start;
if(start==1)
begin
count=count-1;
if(count>1&&count<10) //存储键值
begin
data_ram=data;
i=i+1;
end
else if(count==1)
odd=data;
else if(count==0)
begin
count=11;
i=0;
start=0;
end
else
count=count;
end
else
count=count;
end
always@(negedge start)
begin
led=data_ram; //led是8位的发光二极管,用来显示键码~~
{num_high,num_low}=data_ram;
end
always@(posedge clk) //七段数码管显示部分
begin
cat=~cat;
if(cat==1)
seven(num_high,num);
else
seven(num_low,num);
end
/////////////////////////////////////////////////////////////////////////////
task seven; //数码管显示任务
input num;
output seg_task;
reg seg_reg;
begin
case(num)
4'h0:seg_reg=7'b1000000;
4'h1:seg_reg=7'b1111001;
4'h2:seg_reg=7'b0100100;
4'h3:seg_reg=7'b0110000;
4'h4:seg_reg=7'b0011001;
4'h5:seg_reg=7'b0010010;
4'h6:seg_reg=7'b0000010;
4'h7:seg_reg=7'b1111000;
4'h8:seg_reg=7'b0000000;
4'h9:seg_reg=7'b0010000;
4'ha:seg_reg=7'b0001000;
4'hb:seg_reg=7'b0000000;
4'hc:seg_reg=7'b1000110;
4'hd:seg_reg=7'b1000000;
4'he:seg_reg=7'b0000110;
4'hf:seg_reg=7'b0001110;
default:seg_reg=7'b1111111;
endcase
seg_task=~seg_reg;
end
endtask
endmodule 嗨! LZ 你用的板是自己做的还是买的?我也想学下CPLD 介绍下了 THS! 呵呵 等待楼主学习的新作~ 板是亲戚在XILINX那帮我申请的,X-board,CPLD coolrunner2,这个板自带USB下载,适合我的本本~~哈哈~~ 已经加奇偶校验啦~~不过还是有1%——2%的误码~~
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:44:11 07/22/2008
// Design Name:
// Module Name: PS2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module PS2(data,clock,led,clk,num,cat);
input data;
input clock;
input clk;
output led;
output num;
output cat;
wire data;
wire clock;
wire clk;
reg led;
reg num;
reg cat;
reg data_ram;
reg start;
reg count;
reg i;
reg pass;
reg num_high;
reg num_low;
initial
begin
led=0;
data_ram=0;
start=0;
count=11;
i=0;
num_high=0;
num_low=0;
num=0;
cat=0;
end
always@(negedge clock)
begin
if(data==0)
begin
start=1;
pass=0;
end
else
start=start;
if(start==1)
begin
count=count-1;
if(count>1&&count<10)
begin
data_ram=data;
i=i+1;
end
else if(count==1)
begin
if(data!=^data_ram)
pass=1;
else
pass=0;
end
else if(count==0)
begin
count=11;
i=0;
start=0;
end
else
count=count;
end
else
count=count;
end
always@(negedge start)
begin
if(pass==1)
begin
led=data_ram;
{num_high,num_low}=data_ram;
end
else
led=led;
end
always@(posedge clk)
begin
cat=~cat;
if(cat==1)
seven(num_high,num);
else
seven(num_low,num);
end
/////////////////////////////////////////////////////////////////////////////
task seven;
input num;
output seg_task;
reg seg_reg;
begin
case(num)
4'h0:seg_reg=7'b1000000;
4'h1:seg_reg=7'b1111001;
4'h2:seg_reg=7'b0100100;
4'h3:seg_reg=7'b0110000;
4'h4:seg_reg=7'b0011001;
4'h5:seg_reg=7'b0010010;
4'h6:seg_reg=7'b0000010;
4'h7:seg_reg=7'b1111000;
4'h8:seg_reg=7'b0000000;
4'h9:seg_reg=7'b0010000;
4'ha:seg_reg=7'b0001000;
4'hb:seg_reg=7'b0000000;
4'hc:seg_reg=7'b1000110;
4'hd:seg_reg=7'b1000000;
4'he:seg_reg=7'b0000110;
4'hf:seg_reg=7'b0001110;
default:seg_reg=7'b1111111;
endcase
seg_task=~seg_reg;
end
endtask
endmodule mark 学习
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