同学翻译的UC3AC的datasheet（部分） 大家都来出把力啊！
最近一直关注AVR32，希望能出把力，无奈我的英文太烂了，就找同学帮忙翻译了部分DATASHEET，希望对大家有用。我同学以前没接触过单片机，所以很多地方的翻译有待商榷，有劳前辈们帮忙指正，版主帮忙更新一下。谢谢了。在此特别感谢我的同学
希望大家都能行动起来，把数据手册翻译完整，造福广大的AVR32 fans ！
注： 原文件为：UC3AC_E.PDF
详见： http://www.ouravr.com/bbs/bbs_content.jsp?bbs_sn=995373&bbs_page_no=1&bbs_id=1030 第一个文件 1. Description
The AT32UC3A is a complete System-On-Chip microcontroller based on the AVR32 UC RISC
processor running at frequencies up to 66 MHz. AVR32 UC is a high-performance 32-bit RISC
microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis
on low power consumption, high code density and high performance.
The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller
for supporting modern operating systems and real-time operating systems. Higher
computation capabilities are achievable using a rich set of DSP instructions.
The AT32UC3A incorporates on-chip Flash and SRAM memories for secure and fast access.
For applications requiring additional memory, an external memory interface is provided on
AT32UC3A0 derivatives.
The Peripheral Direct Memory Access controller (PDCA) enables data transfers between peripherals
and memories without processor involvement. PDCA drastically reduces processing
overhead when transferring continuous and large data streams between modules within the
MCU.
The PowerManager improves design flexibility and security: the on-chip Brown-Out Detector
monitors the power supply, the CPU runs from the on-chip RC oscillator or from one of external
oscillator sources, a Real-Time Clock and its associated timer keeps track of the time.
The Timer/Counter includes three identical 16-bit timer/counter channels. Each channel can be
independently programmed to perform frequency measurement, event counting, interval measurement,
pulse generation, delay timing and pulse width modulation.
The PWM modules provides seven independent channels with many configuration options
including polarity, edge alignment and waveform non overlap control. One PWM channel can
trigger ADC conversions for more accurate close loop control implementations.
The AT32UC3A also features many communication interfaces for communication intensive
applications. In addition to standard serial interfaces like UART, SPI or TWI, other interfaces like
flexible Synchronous Serial Controller, USB and Ethernet MAC are available.
The Synchronous Serial Controller provides easy access to serial communication protocols and
audio standards like I2S.
The Full-Speed USB 2.0 Device interface supports several USB Classes at the same time
thanks to the rich End-Point configuration. The On-The-GO (OTG) Host interface allows device
like a USB Flash disk or a USB printer to be directly connected to the processor.
The media-independent interface (MII) and reduced MII (RMII) 10/100 Ethernet MAC module
provides on-chip solutions for network-connected devices.
AT32UC3A integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive
real-time trace, full-speed read/write memory access in addition to basic runtime control.
AT32UC3A
说明：
AT32UC3A是一个支持完整片上系统的微处理器,它基于AVR32 UC RISC处理器,运行频率可达66 MHz. AVR32 UC拥有高性能的32位的微处理器核心,是为费用敏感的嵌入式工程应用而设计，以低功耗，高代码密度和高性能为特点。
它拥有内存保护单元（MPU）和快速而灵活的中断控制器，这样的结构可用于支持现代操作系统和实时操作系统。更高的处理能力使得它可以执行大批DSP指令。
AT32UC3A集成了片内闪存和SRAM用于支持安全而快速的访问。AT32UC3A0系列还提供了外部存储器的接口，用于满足工程上存储器扩展的需要。
外围直接存储器读取控制器(PDCA)可以使数据在外围设备和存储器之间直接传输，不用经过处理器的参与。在MCU内部模块之间传输连续的大块的数据流时，PDCA可以极大的的减少处理器的开销。
电源管理器提高了设计的灵活性和安全性：片上的掉电检测器(BOD)管理着电源的供应，CPU运行的时钟由片上的RC振荡器或一个外部的振荡源提供，内部集成的实时时钟和它的定时器来记录着时间。
定时器/计数器包括三个相同的16位定时器/计数器的通道，每个通道都可以独立编程以执行频率测量，事件计数，间隔测量， 脉冲产生，定时和脉冲宽度调制。
PWM模块，提供了7个独立的通道，这些通道都有很多设置选项，包括极性设置，边沿对准和波形无重叠控制。每个PWM通道都可以触发ADC的转换，以便更精确地实现闭环控制。
AT32UC3A还具有许多通信接口以用于支持各种应用的通信。另外还支持标准的串行接口如UART ， SPI，TWI及其他诸如灵活的同步串行控制器， USB和以太网MAC等接口。
片上的同步串行控制器提供了便捷的串行通信协议和音频标准如I2S。
其集成的全速USB2.0设备接口可以同时支持多种USB类，这是因为它有丰富的端点配置。OTG主机接口允许设备像USB闪存或USB打印机一样直接连接到处理器上。
片上的介质无关接口（MII）和精简的介质无关接口（RMII）10/100M以太网MAC模块为网络设备的通信提供了一个片上的解决方案。
AT32UC3A集成了支持Nexus Class 2+协议的片上仿真系统，除了基本的运行控制外，还有非侵入式实时跟踪，全速读/写存储器功能。 13. Power Manager (PM)
Rev: 2.0.0.1
13.1 Features
• Controls integrated oscillators and PLLs
• Generates clocks and resets for digital logic
• Supports 2 crystal oscillators 450 kHz-16 MHz
• Supports 2 PLLs 80-240 MHz
• Supports 32 KHz ultra-low power oscillator
• Integrated low-power RC oscillator
• On-the fly frequency change of CPU, HSB, PBA, and PBB clocks
• Sleep modes allow simple disabling of logic clocks, PLLs, and oscillators
• Module-level clock gating through maskable peripheral clocks
• Wake-up from internal or external interrupts
• Generic clocks with wide frequency range provided
• Automatic identification of reset sources
• Controls brownout detector (BOD), RC oscillator, and bandgap voltage reference through control
and calibration registers
13.2 Description
The Power Manager (PM) controls the oscillators and PLLs, and generates the clocks and
resets in the device. The PM controls two fast crystal oscillators, as well as two PLLs, which can
multiply the clock from either oscillator to provide higher frequencies. Additionally, a low-power
32 KHz oscillator is used to generate the real-time counter clock for high accuracy real-time
measurements. The PM also contains a low-power RC oscillator with fast start-up time, which
can be used to clock the digital logic.
The provided clocks are divided into synchronous and generic clocks. The synchronous clocks
are used to clock the main digital logic in the device, namely the CPU, and the modules and
peripherals connected to the HSB, PBA, and PBB buses. The generic clocks are asynchronous
clocks, which can be tuned precisely within a wide frequency range, which makes them suitable
for peripherals that require specific frequencies, such as timers and communication modules.
The PM also contains advanced power-saving features, allowing the user to optimize the power
consumption for an application. The synchronous clocks are divided into three clock domains,
one for the CPU and HSB, one for modules on the PBA bus, and one for modules on the PBB
bus.The three clocks can run at different speeds, so the user can save power by running peripherals
at a relatively low clock, while maintaining a high CPU performance. Additionally, the
clocks can be independently changed on-the-fly, without halting any peripherals. This enables
the user to adjust the speed of the CPU and memories to the dynamic load of the application,
without disturbing or re-configuring active peripherals.
Each module also has a separate clock, enabling the user to switch off the clock for inactive
modules, to save further power. Additionally, clocks and oscillators can be automatically
switched off during idle periods by using the sleep instruction on the CPU. The system will return
to normal on occurrence of interrupts.
The Power Manager also contains a Reset Controller, which collects all possible reset sources,
generates hard and soft resets, and allows the reset source to be identified by software.
电源管理
特点:
1. 集成可控的振荡器和锁相环
2. 可为数字逻辑产生时钟和复位
3. 可支持2个450K-16MHz的晶振
4. 支持2个80-240MHz的plls
5. 集成32KHz的超低功耗振荡器
6. 片内集成低功耗RC振荡器
7. 支持CPU, HSB, PBA,和PBB的动态频率修改
8. 睡眠模式下允许逻辑时钟，plls和振荡器处在简单禁用状态
9. 在可屏蔽的时钟中可进行模块级时钟门控
10. 支持内部或外部中断唤醒功能
11. 对通用时钟有很宽的频率范围支持
12. 拥有自动鉴别复位源功能
13. 片内集成BOD，RC振荡器，还有通过控制和校准记录设定带隙基准电压的功能
描述：
电源管理器（PM）控制振荡器和plls，并在设备中产生时钟和复位信号。它控制两个高速的晶体振荡器和两片PLLs,这样可以从任一振荡器中得到倍乘的时钟用以提供更高的频率。另外，片内集成的一个低功耗32KHz的振荡器可以产生实时计数器时钟以用于实现更高精度的实时时间测量。电源管理器也集成了一个低功耗的RC振荡器，它有极短的启动时间，可被用来计时数字逻辑。
提供的时钟被分为同步时钟和通用时钟。其中的同步时钟用来为设备中的主要数字逻辑提供时钟信号，也就是CPU，各个模块以及连接到HSB, PBA和PBB总线上的外围设备。通用时钟是异部的时钟信号，可以在很宽的频率范围内被精确调谐，这使得他们很适合为定时器和通信模块这样的外围设备提供时钟信号，因为这些设备需要专门的频率。
电源管理器也有先进的省电功能，这使得用户可以优化应用程序中的电源消耗情况。同步时钟信号被分为三个时钟域，一个用来支持CPU和HSB，另一个用来支持PBA总线上的模块，最后一个用来支持PBB总线上的模块。这三个时钟可以运行在不同速度上，使得用户可以将外围设备运行在一个相对较低的时钟上来达到省电的目的，而又能保持较高的CPU性能。此外可以独立动态的改变时钟而不用中止外围设备的运作。这使得用户可以在不干扰或重新配置正在工作的外围设备的情况下，调整CPU和存储器的速度以达到动态装载应用程序的目的。
每个模块也有各自的时钟，用户可以关闭未运行模块的时钟以进一步节省电能。此外，当CPU接到睡眠指令进入空闲期时，时钟和振荡器可被自动关闭，但是当发生中断事件时，系统可以返回到正常状态。
电源管理器也集成了一个复位控制器，可以收集一切可能的复位源发出的信号，产生硬复位或软复位，但是复位源也可以通过软件来过滤选择。 14. Real Time Counter (RTC)
Rev: 2.3.0.1
14.1 Features
• 32-bit real-time counter with 16-bit prescaler
• Clocked from RC oscillator or 32 KHz oscillator
• High resolution: Max count frequency 16 KHz
• Long delays
– Max timeout 272 years
• Extremely low power consumption
• Available in all sleep modes except Static
• Optional wrap at max value
• Interrupt on wrap
14.2 Description
The Real Time Counter (RTC) enables periodic interrupts at long intervals, or accurate measurement
of real-time sequences. The RTC is fed from a 16-bit prescaler, which is clocked from
the RC oscillator or the 32 KHz oscillator. Any tapping of the prescaler can be selected as clock
source for the RTC, enabling both high resolution and long timeouts. The prescaler cannot be
written directly, but can be cleared by the user.
The RTC can generate an interrupt when the counter wraps around the value stored in the top
register, producing accurate periodic interrupts.
实时计数器(RTC)
特点:
1. 集成带有16位预分频器的32位的实时计数器
2. 片内集成的RC振荡器或32K的越低功耗振荡器提供时钟信号
3. 计数精度高：最高计数频率可达16KHz
4. 定时时间长-最长定时时间达272年
5. 电能消耗极低
6. 除静态模式外可在所有的睡眠模式中使用
7. Optional wrap at max value
8. Interrupt on wrap
描述：
实时计数器（RTC）可以在一个较长的时间间隔内实现周期性的中断，也可以实现实时序列的精确测量。RTC的时钟由一个16位的预分频器提供，这个预分频器的时钟又是由片内集成的RC振荡器或32KHz的低功耗振荡器产生。
每一个预分频器的信号都可以被选择作为RTC的时钟源，这保证它既有高的分辨率也有较长的延迟时间。
但是预分频器不能被直接设定写入初始值，但是可以被用户清零。当计数器达到预定的最高值时，RTC可以产生一个中断，也可以产生精确的周期性的中断。 15. Watchdog Timer (WDT)
Rev: 2.3.0.1
15.1 Features
• Watchdog Timer counter with 16-bit prescaler
• Clocked from RC oscillator
15.2 Description
The Watchdog Timer (WDT) has a prescaler generating a timeout period. This prescaler is
clocked from the RC oscillator. The watchdog timer must be periodically reset by software within
the timeout period, otherwise, the device is reset and starts executing from the boot vector. This
allows the device to recover from a condition that has caused the system to be unstable.
看门狗定时器（WDT）
特点：
1． 集成带有一个16位预分频器的看门狗定时器。
2． 由RC振荡器提供时钟信号。
描述：
看门狗定时器（WDT）有一个预分频器用来产生延时，这个预分频器是由片内的RC振荡器提供时钟信号。看门狗定时器必须在延迟时间内由软件进行周期性的复位，否则，设备将会复位并从启动向量处开始执行。由此可见，它可以使设备从一个造成系统不稳定的因素中恢复过来。 16. Interrupt Controller (INTC)
Rev: 1.0.1.1
16.1 Description
The INTC collects interrupt requests from the peripherals, prioritizes them, and delivers an interrupt
request and an autovector to the CPU. The AVR32 architecture supports 4 priority levels for
regular, maskable interrupts, and a Non-Maskable Interrupt (NMI).
The INTC supports up to 64 groups of interrupts. Each group can have up to 32 interrupt request
lines, these lines are connected to the peripherals. Each group has an Interrupt Priority Register
(IPR) and an Interrupt Request Register (IRR). The IPRs are used to assign a priority level and
an autovector to each group, and the IRRs are used to identify the active interrupt request within
each group. If a group has only one interrupt request line, an active interrupt group uniquely
identifies the active interrupt request line, and the corresponding IRR is not needed. The INTC
also provides one Interrupt Cause Register (ICR) per priority level. These registers identify the
group that has a pending interrupt of the corresponding priority level. If several groups have an
pending interrupt of the same level, the group with the lowest number takes priority.
中断控制器（INTC）
描述：
中断控制器（INTC）从外围设备中收集中断请求，判别它们的优先级，然后把中断请求和自动向量传送给CPU。该AVR32的架构为定期中断，屏蔽中断和非屏蔽中断（NMI）提供4个层次的中断优先等级。
该中断控制器支持多达64组的中断，每组最多有32个中断请求线，这些中断请求线是连接到外围设备的。每级都有一个中断优先级寄存器（IPR）和一个中断请求寄存器（IRR），IPR是用来为每组分配一个优先级水平和一个自动向量，而IRR是用来识别每组内活动的中断请求的。如果一组只有一个中断请求线，那么活动的中断组就唯一认定该活跃的中断请求线，其他相同的IRR就不需要了。INTC也为每个优先级的中断提供了一个中断成因寄存器（ICR），这些寄存器用于识别那些中断组，这些中断组有处在同一中断优先级而挂起未决的中断。如果一些组有一些处在同一优先级的未决的中端，那么最低号码的组有最高的优先级。 17. External Interrupts Controller (EIC)
Rev: 2.3.0.1
17.1 Features
• Dedicated interrupt requests for each interrupt
• Individually maskable interrupts
• Interrupt on rising or falling edge
• Interrupt on high or low level
• Asynchronous interrupts for sleep modes without clock
• Filtering of interrupt lines
• Keypad scan support
• Maskable NMI interrupt
17.2 Description
The External Interrupt Module allows pins to be configured as external interrupts. Each pin has
its own interrupt request and can be individually masked. Each pin can generate an interrupt on
rising or falling edge, or high or low level. Every line has a configurable filter too remove spikes
on the interrupt lines. Every interrupt pin can also be configured to be asynchronous to wake up
the part from sleep modes where the clock has been disabled.
A Non-Maskable Interrupt (NMI) is also supported. This has the same properties as the other
external interrupts, but is connected to the NMI request of the CPU, enabling it to interrupt any
other interrupt mode.
The External Interrupt Module has support for keypad scanning for keypads laid out in rows and
columns. Columns are driven by a separate set of scanning outputs, while rows are sensed by
the external interrupt lines. The pressed key will trigger an interrupt, which can be identified
through the user registers of the module.
The External Interrupt Module can wake up the part from sleep modes without triggering an
interrupt. In this mode, code execution starts from the instruction following the sleep instruction.
外部中断控制器（EIC）
特点：
1.为每个中断提供专门的中断请求
2.支持个别可屏蔽中断
3.支持上升沿中断或下降沿中断
4.中断支持高低优先级
5.可进行异步中断，用于支持无时钟的睡眠模式。
6.支持中断线的过滤
7.支持键区扫描
8.支持可屏蔽中断和非可屏蔽中断
描述：
外部中断控制器(EIC)模块也允许管脚被配置为外部中断。每个管脚都有自己的中断请求，并且可以被独立屏蔽。每个管脚都可以在上升沿或下降沿产生优先级不同的中断。每个管脚都有一个可配置的过滤器用于滤除中断线上的毛刺。每个中断管脚也可以被设置为异步模式，用于唤醒时钟被关闭的处于睡眠模式的部分。
EIC也支持非屏蔽中断（NMI）。该非屏蔽中断与其他外部中断有相同的参数，但是是被连接到CPU的NMI请求上，这使得它能够中断其他的外部中断模式。
外部中断模块也支持键盘扫描，用于支持行列键盘。键盘的列由独立的一套扫描信号来驱动而行是通过外部中断线来传感。压下的键将会触发一个中断，这样就可以通过模块中所存的用户的记录来识别方位。
外部中断模块也可以不触发中断而唤醒处于睡眠模式的部分。这在种模式下，代码是从处于睡眠指令以后的代码处执行。 18. Flash Controller (FLASHC)
Rev: 2.0.0.1
18.1 Features
• Controls flash block with dual read ports allowing staggered reads.
• Supports 0 and 1 wait state bus access.
• Allows interleaved burst reads for systems with one wait state, outputting one 32-bit word per
clock cycle.
• 32-bit HSB interface for reads from flash array and writes to page buffer.
• 32-bit PB interface for issuing commands to and configuration of the controller.
• 16 lock bits, each protecting a region consisting of (total number of pages in the flash block /
16) pages.
• Regions can be individually protected or unprotected.
• Additional protection of the Boot Loader pages.
• Supports reads and writes of general-purpose NVM bits.
• Supports reads and writes of additional NVM pages.
• Supports device protection through a security bit.
• Dedicated command for chip-erase, first erasing all on-chip volatile memories before erasing
flash and clearing security bit.
• Interface to Power Manager for power-down of flash-blocks in sleep mode.
18.2 Description
The flash controller (FLASHC) interfaces a flash block with the 32-bit internal HSB bus. Performance
for uncached systems with high clock-frequency and one wait state is increased by
placing words with sequential addresses in alternating flash subblocks. Having one read interface
per subblock allows them to be read in parallel. While data from one flash subblock is
being output on the bus, the sequential address is being read from the other flash subblock
and will be ready in the next clock cycle.
The controller also manages the programming, erasing, locking and unlocking sequences with
dedicated commands.
闪存控制器（FLASHC）
特点：
1． 闪存控制区拥有双重读端口，允许交错式读取。
2． 支持处于0和1等待状态的总线读取。
3． 允许交叉成组式的读取方式用于支持处于一个等待周期的系统，它可以在每个时钟周期输出一个32位的字。
4． 集成32位的HSB接口用于支持闪存阵列的读取,也支持向页缓冲区的写入
5． 集成32位的PB接口用于支持传送命令和控制器的配置信息
6． 16个锁定位,每个都可以保护构成页面(闪存区的总页面数/16)的区域
7． 区域也可以被各自保护和不保护
8． 对启动装载的页面有另外的保护
9． 支持对通用NVM位的读写
10． 支持对附加NVM页面的读写
11． 可以通过安全位来保护设备
12． 有专门的芯片擦除命令，擦除时，在清除安全位和擦除闪存区前，首先擦去芯片上的所有易失性数据
13． 集成电源管理器接口，用于解决处于睡眠模式下闪存区的电源故障
描述：
闪存控制器（FLASHC）用来为有32位内部HSB总线的闪存区提供接口。通过在交替的闪存附属区放置地址连续的字,拥有很高的时钟频率和一个等待状态的无缓存系统的性能得到很大的提升。每个附属区有一个读接口，这使得它们可以被平行读取。当一个闪存附属区的数据输出到总线上时，它们那些连续的地址在下一个时钟周期也会从另一个闪存附属区上被准备好。
闪存控制器还管理编程，擦除，锁定和解锁由专用命令控制的序列。 19.1 Features
• User Interface on peripheral bus
• Configurable Number of Masters (Up to sixteen)
• Configurable Number of Slaves (Up to sixteen)
• One Decoder for Each Master
• Three Different Memory Mappings for Each Master (Internal and External boot, Remap)
• One Remap Function for Each Master
• Programmable Arbitration for Each Slave
– Round-Robin
– Fixed Priority
• Programmable Default Master for Each Slave
– No Default Master
– Last Accessed Default Master
– Fixed Default Master
• One Cycle Latency for the First Access of a Burst
• Zero Cycle Latency for Default Master
• One Special Function Register for Each Slave (Not dedicated)
19.2 Description
The Bus Matrix implements a multi-layer bus structure, that enables parallel access paths
between multiple High Speed Bus (HSB) masters and slaves in a system, thus increasing the
overall bandwidth. The Bus Matrix interconnects up to 16 HSB Masters to up to 16 HSB Slaves.
The normal latency to connect a master to a slave is one cycle except for the default master of
the accessed slave which is connected directly (zero cycle latency). The Bus Matrix provides 16
Special Function Registers (SFR) that allow the Bus Matrix to support application specific
features.
HSB总线矩阵（HMATRIX）
特点：
1． 支持在外围总线上的用户接口
2． 可配置的总机数量达到16个
3． 可配置的从从机数量达到16个
4． 每个主机都有一个编码器
5． 三个不同的存储器为每个主机映射（可从内部和外部启动，重映射）
6． 每个主机都有重映射功能
7． 可为每个从机编程仲裁-轮流式或固定优先级式
8． 每个从机都有可编程的和默认的主机，包括：无默认主机，上次接通的主机，固定默认的主机
9． 对一组数据的首次访问有一个周期的延迟
10． 对默认主机的访问有零周期的延迟
11． 每个从机都有一个特殊功能寄存器
描述：
该总线矩阵实现了一个多层的总线结构，这使得多个高速总线主机和从机之间的平行访问路径处在同个系统中，从而增加了总体的宽带。总线矩阵使多达16个HSB主机和16个HSB从机相连在一起。主机和从机连接的正常延迟是一个时钟周期，但是默认主机和它的从机是直接连接的，延迟时间为零个时钟周期。总线矩阵提供了16个特殊功能寄存器（SFR），使得它能支持工程上的特殊的应用特性。 20. External Bus Interface (EBI)
Rev: 1.0.0.1
20.1 Features
• Present only on AT32UC3A0512 and AT32UC3A0256
• Optimized for Application Memory Space support
• Integrates Two External Memory Controllers:
– Static Memory Controller
– SDRAM Controller
• Optimized External Bus:
– 16-bit Data Bus
– 24-bit Address Bus, Up to 16-Mbytes Addressable
– Optimized pin multiplexing to reduce latencies on External Memories
• 4 SRAM Chip Selects, 1 SDRAM Chip Selects:
– Static Memory Controller on NCS0
– SDRAM Controller or Static Memory Controller on NCS1
– Static Memory Controller on NCS2
– Static Memory Controller on NCS3
20.2 Description
The External Bus Interface (EBI) is designed to ensure the successful data transfer between
several external devices and the AT32UC3A device. The Static Memory and SDRAM Controllers
are all featured external Memory Controllers on the EBI. These external Memory Controllers
are capable of handling several types of external memory and peripheral devices, such as
SRAM, PROM, EPROM, EEPROM, Flash, and SDRAM.
The EBI handles data transfers with up to five external devices, each assigned to five address
spaces defined by the embedded Memory Controller. Data transfers are performed through a
16-bit data bus, an address bus of up to 24 bits, up to four chip select lines (NCS) and several
control pins that are generally multiplexed between the different external Memory
Controllers.
外部总线接口（EBI）
特点：
1． 仅在AT32UC3A0512和AT32UC3A0256上支持
2． 支持应用程序存储器空间的优化
3． 集成两个外部存储器控制器（静态存储器控制器和SDRAM控制器）
4． 外部总线经过优化：-16位数据总线
-24位数据总线，可寻址范围达16M
-优化了管脚复用技术以减少外部存储器的延迟
5．集成4个SRAM芯片和一个SDRAM芯片
-NCS0上集成的静态存储器控制器
-NCS1上的SDRAM控制器或静态存储器控制器
-NCS2上的静态存储器控制器
-NCS3上的静态存储器控制器
描述：
外部总线接口(EBI)的设计是用来保证一些外部设备与at32uc3a设备之间数据传送成功。静态存储器控制器和SDRAM控制器都是作为EBI上的外部存储器控制器来看待的。这些外部存储器控制器可以管理好几种外部存储器和外围设备如SRAM，PROM，EPROM，EEPROM，Flash和SDRAM。
EBI可以与多达5个外部设备进行数据传输，每个都被分配到由嵌入式存储器控制器所定义的5个地址空间上。数据传输是通过一条16位的数据总线，一条多达24位的地址总线，和多达4个芯片选择线路（NCS）及一些控制管脚来进行，而这些控制管脚在不同的外部存储器控制器之间是可以复用的。 21. Peripheral DMA Controller (PDCA)
rev: 1.0.0.0
21.1 Features
• Generates Transfers to/from Peripherals such as USART, SSC and SPI
• Two address pointers/counters per channel allowing double buffering
21.2 Overview
The Peripheral DMA controller (PDCA) transfers data between on-chip peripheral modules such
as USART, SPI, SSC and on- and off-chip memories. Using the PDCA avoids CPU intervention
for data transfers, improving the performance of the microcontroller. The PDCA can transfer
data from memory to a peripheral or from a peripheral to memory.
The PDCA consists of a number of DMA channels. Each channel has:
• A 32-bit memory pointer
• A 16-bit transfer counter
• A 32-bit memory pointer reload value
• A 16-bit transfer counter reload value
The PDCA communicates with the peripheral modules over a number of handshake interfaces.
The peripheral signals to the PDCA when it is ready to receive or transmit data. The PDCA
acknowledges the request when the transmission has started.
The number of handshake-interfaces may be higher than the number of DMA channels. If this is
the case, the DMA channel must be programmed to use the desired interface.
When a transmit buffer is empty or a receive buffer is full, an interrupt request can be signalled.
外围DMA控制器（PDCA）
特点：
1． 能够向或从储如USART，SSC和SPI这些外围设备传输数据
2． 有2地址指针/计数器，每个通道允许双缓冲
概览：
外围DMA控制器（PDCA）在储如USART，SPI，SSC等片上的外围模块和片外存储器之间传送数据。使用PDCA可以阻止数据传送时CPU的介入从而大大增加了微处理器的性能。PDCA可以从存储器到外围设备也可以从外围设备到存储器传送数据。
PDCA由很多DMA通道组成，每个通道都有：1.一个32位的内存指针
2.一个16位的传送计数器
3.一个32位的内存指针重装值
4.一个16位的传送计数器重装值
PDCA与外围模块的通信是通过一系列信号交换接口来实现的。外围设备准备好发送或接收数据时会向PDCA传送信号，PDCA会应答请求当传送已经开始时。
信号交换接口的数量可能会比DMA通道的数量多，在这种情况下，DMA通道必须被编程去使用所需的接口。
传送缓冲区空或接收缓冲区满时就会发出一个中断信号。 22. General-Purpose Input/Output Controller (GPIO)
Rev. 1.1.0.2
22.1 Features
Each I/O line of the GPIO features:
• Configurable pin-change, rising-edge or falling-edge interrupt on any I/O line.
• A glitch filter providing rejection of pulses shorter than one clock cycle.
• Open Drain mode enabling sharing of an I/O line between the MCU and external components.
• Input visibility and output control.
• Multiplexing of up to four peripheral functions per I/O line.
• Programmable internal pull-up resistor.
22.2 Overview
The General Purpose Input/Output manages the I/O pins of the microcontroller. Each I/O line
may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral.
This assures effective optimization of the pins of a product.
通用I/O控制器（GPIO）
特点：
每个GPIO的I/O线的特点是：
1． 管脚改变是可以配置的，每个I/O线都支持上升沿中断和下降沿中断。
2． 故障过滤器可以拒绝时间长度小于一个时钟周期的脉冲所发出的请求。
3． 耗尽模式打开后可以使MCU和外部元件之间实现I/O线共享。
4． 支持输入可见和输出控制。
5． 每个I/O线最多复用4个外设功能
6． 内部集成可编程的上拉电阻
总览：
通用I/O管理着微控制器的I/O管脚,每个I/O线可以被专用为一个通用的I/O管脚,也可以被分配给一个嵌入式设备作为其功能的一部分使用。这保证了产品管脚的有效优化。 23. Serial Peripheral Interface (SPI)
Rev: 1.9.9.3
23.1 Features
• Supports Communication with Serial External Devices
– Four Chip Selects with External Decoder Support Allow Communication with Up to 15
Peripherals
– Serial Memories, such as DataFlash and 3-wire EEPROMs
– Serial Peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors
– External Co-processors
• Master or Slave Serial Peripheral Bus Interface
– 8- to 16-bit Programmable Data Length Per Chip Select
– Programmable Phase and Polarity Per Chip Select
– Programmable Transfer Delays Between Consecutive Transfers and Between Clock and Data
Per Chip Select
– Programmable Delay Between Consecutive Transfers
– Selectable Mode Fault Detection
• Connection to PDC Channel Capabilities Optimizes Data Transfers
– One Channel for the Receiver, One Channel for the Transmitter
– Next Buffer Support
23.2 Description
The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication
with external devices in Master or Slave Mode. It also enables communication
between processors if an external processor is connected to the system.
The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to
other SPIs. During a data transfer, one SPI system acts as the “master”' which controls the data
flow, while the other devices act as “slaves'' which have data shifted into and out by the master.
Different CPUs can take turn being masters (Multiple Master Protocol opposite to Single Master
Protocol where one CPU is always the master while all of the others are always slaves) and one
master may simultaneously shift data into multiple slaves. However, only one slave may drive its
output to write data back to the master at any given time.
A slave device is selected when the master asserts its NSS signal. If multiple slave devices
exist, the master generates a separate slave select signal for each slave (NPCS).
The SPI system consists of two data lines and two control lines:
• Master Out Slave In (MOSI): This data line supplies the output data from the master shifted
into the input(s) of the slave(s).
• Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of
the master. There may be no more than one slave transmitting data during any particular
transfer.
• Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data
bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once for
each bit that is transmitted.
• Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.
串行外设接口（SPI）
特点：
1.支持与外部串行设备的通信：
-有4芯片可供选择，并有外部解码器的支持使得可以与多达15个外部的设备进行通信
-支持串行存储器如数据闪存区和3线的EEPROM
-支持串行设备如ADC，DAC，LCD控制器，CAN控制器和传感器
-支持外部协处理器
2.集成有主机或从机串行外设总线接口
-每个可选择的芯片支持8到16位的可编程的数据长度
-每个可选芯片的相位和极性都支持编程
-每个可选芯片在连续的传送数据之间及在时钟和数据之间,其传送延迟都是可编程的
-在连续的传送时延迟是可编程的
-支持可选模式的故障检测
拥有连接到PDC通道的能力从而优化数据传送
-一个通道是为接收器,一个通道是为发射机
-也支持次缓冲区
描述:
该串行外设接口电路是一个同步串行数据链路,能为处在主机或从机模式的外部设备提供通信,如果有外部的处理器连接到系统上,它也可以为处理器之间提供通信。
该串行外设接口本质上是一个串行移位寄存器即逐位的传送数据位到其他的SPI上。在数据传送期间，该SPI系统作为一个主设备用来控制数据流，而其他的设备则作为从设备，使数据移入或移出是由主设备控制。
不同的CPU之间可以轮流作为主设备（多个主设备的协议与单个主设备的协议是相对的，因为其中一个CPU始终是主设备，而其他的CPU始终是从设备）一个主设备也可以同时把数据移动到多重从设备中去。然而在任何给定的时间内只有一个从设备可以驱动它的输出信号并写入数据回馈到主设备。
当主机发出它的NSS信号时一个从设备可以被选定，当有多个从设备存在时，主设备会为每个从设备产生一个独立的选择信号（NPCS）。
SPI系统是由两个数据线和两个控制线组成的。
1． 主设备出从设备进（MOSI）：这个数据线是用来把从主设备输出的数据移入从设备输入。
2． 主设备进从设备出（MISO）：这个数据线是用来把一个从设备输出的数据供给主设备输入，在特定的传输情况下，可能没有一个从设备传送数据。
3． 串行时钟（SPCK）：这个控制线是由主设备驱动用来有系统地管理数据位流。主设备可能会通过多样的波特率来发射数据；每个被发射的数据位占用SPCK的线上的一个周期。
4． 从设备选择（NSS）：这个控制线允许从设备被硬件打开或关闭。 24. Two-Wire Interface (TWI)
2.1.1.0
24.1 Features
• Compatible with Atmel Two-wire Interface Serial Memory and I²C Compatible Devices(1)
• One, Two or Three Bytes for Slave Address
• Sequential Read-write Operations
• Master, Multi-master and Slave Mode Operation
• Bit Rate: Up to 400 Kbits
• General Call Supported in Slave mode
• Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers in
Master Mode Only
– One Channel for the Receiver, One Channel for the Transmitter
– Next Buffer Support
Note: 1. See Table 24-1 below for details on compatibility with I²C Standard.
24.2 Overview
The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made
up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a
byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial
EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD
Controllers and Temperature Sensor, to name but a few. The TWI is programmable as a master
or a slave with sequential or single-byte access. Multiple master capability is supported. Arbitration
of the bus is performed internally and puts the TWI in slave mode automatically if the bus
arbitration is lost.
A configurable baud rate generator permits the output data rate to be adapted to a wide range of
core clock frequencies.
Below, Table 24-1 lists the compatibility level of the Atmel Two-wire Interface in Master Mode and
a full I2C compatible device.
双线接口（TWI）
特点：
1． 兼容梅尔双线接口串行存储器和与I²C兼容的设备。
2． 为每个从属的地址提供1，2，或3个字节的支持。
3． 支持连续的读写操作
4． 支持主设备，多重主设备和从设备模式操作
5． 比特率：多达400Kbit/s
6． 支持在从设备模式下的通用调用
7． 拥有连接到外围DMA控制器通道的能力从而优化数据传送，但是只在设备模式下可用
-一个通道用于接收器，一个通道用于发射器
-支持次缓冲区
总览：
该梅尔双线接口（TWI）使组件互连在一个独特的双线总线上，而该总线是由一个时钟线和一个数据线组成，传输速度高达400Kbit/s，且是基于字节导向的传送格式。它可以与任何梅尔双线接口总线串行EEPROM和I²C兼容设备如实时时钟，点矩阵/图形LCD控制器和温度传感器等一块使用。TWI可以被编程作为主设备或从设备进行连续或单字节访问。多重主设备也是支持的。总线上的仲裁是在内部进行的，如果总线仲裁功能失效TWI将会自动被置于从设备模式下。
一个可配置的波特率发生器的输出数据率可被更改到一个更宽的时钟频率范围。 25. Synchronous Serial Controller (SSC)
Rev: 3.1.0.1
25.1 Features
• Provides Serial Synchronous Communication Links Used in Audio and Telecom Applications
• Contains an Independent Receiver and Transmitter and a Common Clock Divider
• Interfaced with Two PDC Channels (DMA Access) to Reduce Processor Overhead
• Offers a Configurable Frame Sync and Data Length
• Receiver and Transmitter Can be Programmed to Start Automatically or on Detection of Different
Events on the Frame Sync Signal
• Receiver and Transmitter Include a Data Signal, a Clock Signal and a Frame Synchronization
Signal
25.2 Description
The Atmel Synchronous Serial Controller (SSC) provides a synchronous communication link
with external devices. It supports many serial synchronous communication protocols generally
used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc.
The SSC contains an independent receiver and transmitter and a common clock divider. The
receiver and the transmitter each interface with three signals: the TD/RD signal for data, the
TK/RK signal for the clock and the TF/RF signal for the Frame Sync. The transfers can be programmed
to start automatically or on different events detected on the Frame Sync signal.
The SSC’s high-level of programmability and its two dedicated PDC channels of up to 32 bits
permit a continuous high bit rate data transfer without processor intervention.
Featuring connection to two PDC channels, the SSC permits interfacing with low processor
overhead to the following:
• CODEC’s in master or slave mode
• DAC through dedicated serial interface, particularly I2S
• Magnetic card reader
同步串行控制器（SSC）
特点：
1． 支持串行同步通信链路在声音或电信应用中
2． 包含一个独立的接收器和发射器及一个普通的时钟分配器
3． 与两个PDC通道有接口（DMA式访问）用于减少处理器的介入
4． 提供一个可编程的帧同步方式和数据长度
5． 接收机和发射机可以被编程自动开始或检测到帧同步信号上的非寻常事件后启动
6． 接收机和发射机包括一个数据信号，一个时钟信号，一个帧同步信号
描述：
该梅尔同步串行控制器（SSC）提供了一个与外部设备的同步通信链路。它支持很多音频和电信应用上的串行同步通信协议如I2S，短帧同步，长帧同步，等等。
SSC包含一个独立的接收器和发射器及一个时钟分频器。那个接收器和发射器的每个接口有三个信号：用于数据的TD/RD信号，用于时钟的TK/RK信号和用于帧同步的TF/RF信号。发射机可以被编程自动开始或检测到帧同步信号上的非寻常事件后启动。
SSC的高级别的可编程性及它的两个高达32位的专用PDC通道可以进行连续高比特率的数据传输而不经过处理器的干预。
由于连接到两个PDC通道，SSC允许接口在如下情况下使处理器很少介入：
1．编解码器工作在主或从模式下
2．工作在专用串行接口的DAC，特别是I2S
3．磁卡阅读器 26. Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
Rev. 4.0.0.1
26.1 Features
• Programmable Baud Rate Generator
• 5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications
– 1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous Mode
– Parity Generation and Error Detection
– Framing Error Detection, Overrun Error Detection
– MSB- or LSB-first
– Optional Break Generation and Detection
– By 8 or by 16 Over-sampling Receiver Frequency
– Optional Hardware Handshaking RTS-CTS
– Receiver Time-out and Transmitter Timeguard
– Optional Multidrop Mode with Address Generation and Detection
• RS485 with Driver Control Signal
• ISO7816, T = 0 or T = 1 Protocols for Interfacing with Smart Cards
– NACK Handling, Error Counter with Repetition and Iteration Limit
• IrDA Modulation and Demodulation
– Communication at up to 115.2 Kbps
• SPI Mode
– Master or Slave
– Serial Clock Programmable Phase and Polarity
– SPI Serial Clock (SCK) Frequency up to Internal Clock Frequency MCK/4
• Test Modes
– Remote Loopback, Local Loopback, Automatic Echo
• Supports Connection of Two Peripheral DMA Controller Channels (PDC)
– Offers Buffer Transfer without Processor Intervention
26.2 Overview
The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full
duplex universal synchronous asynchronous serial link. Data frame format is widely programmable
(data length, parity, number of stop bits) to support a maximum of standards. The receiver
implements parity error, framing error and overrun error detection. The receiver time-out enables
handling variable-length frames and the transmitter timeguard facilitates communications with
slow remote devices. Multidrop communications are also supported through address bit handling
in reception and transmission.
The USART features three test modes: remote loopback, local loopback and automatic echo.
The USART supports specific operating modes providing interfaces on RS485 and SPI buses,
with ISO7816 T = 0 or T = 1 smart card slots and infrared transceivers. The hardware handshaking
feature enables an out-of-band flow control by automatic management of the pins RTS and
CTS.
The USART supports the connection to the Peripheral DMA Controller, which enables data
transfers to the transmitter and from the receiver. The PDC provides chained buffer management
without any intervention of the processor.
通用同步/异步接收机/发射机(USART)
特点:
1. 集成可编程的波特率产生器
2. 支持5位到9位全双工同步或异步串行通信
-异步模式下有1,1.5或者2个停止位,同步模式下有1或2个停止位
-有奇偶发生和错误检测功能
-有帧错误检测和超越误差检测功能
-可选从最高位或从最低位开始
-可选的间或产生或检测功能
-支持8倍或16倍的过采样接收频率
-可选的硬件流RTS-CTS
-支持接收机时间超时和发射机的时间守护功能
-可选的多站模式,并有地址产生和检测功能
3.支持带有驱动控制信号的RS485
4.支持ISO7816,T=0或T=1协议,用于为智能卡提供接口
5.支持IrDA调制和解调-通信速度达115.2Kbps
6.支持SPI模式-主设备或从设备
-支持中午时钟的相位编程和极性编程
-SPI串行时钟频率可达到内部时钟频率MCK/4
7．测试模式：-支持远程回送，本地回送，自动显示
8．支持连接到两个外围DMA控制器通道上（PDC）-支持没有处理器介入的缓冲区传送
总览：
通用同步异步接收收发器（USART ）提供了一个充分全双工通用同步异步串行链接。数据帧格式是广泛的可编程（数据长度，奇偶数，停止位） ，以支持最多的标准。接收器实行奇偶错误检测，帖错误检测，和超支的错误检测。接收机的超时使在与缓慢的远程设备通信时处理可变长度的帧和发射机的时间指示变得容易。多点通信也是支持的通过在接收和传输时的地址位。
USART提供了三种测试模式：远程回送，本地回送和自动显示。
USART也支持具体操作模式，用于为带有ISO7816 T=0或T=1智能卡槽和红外线接收器的RS485和SPI总路线提供接口。
USART支持连接到外围DMA控制器，这使得数据可以传送到发射机或从接收器传出来。在没有任何处理器介入的情况下，PDC支持提供链接的缓冲区管理功能。 27. Static Memory Controller (SMC)
Rev: 1.0.4.2
27.1 Features
• 4 Chip Selects Available
• 64-Mbyte Address Space per Chip Select
• 8-, 16- or 32-bit Data Bus
• Word, Halfword, Byte Transfers
• Byte Write or Byte Select Lines
• Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select
• Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select
• Programmable Data Float Time per Chip Select
• Compliant with LCD Module
• External Wait Request
• Automatic Switch to Slow Clock Mode
• Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes
27.2 Description
The Static Memory Controller (SMC) generates the signals that control the access to the external
memory devices or peripheral devices. It has 4 Chip Selects and a 26-bit address bus. The
32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. Separate
read and write control signals allow for direct memory and peripheral interfacing. Read and write
signal waveforms are fully parametrizable.
The SMC can manage wait requests from external devices to extend the current access. The
SMC is provided with an automatic slow clock mode. In slow clock mode, it switches from userprogrammed waveforms to slow-rate specific waveforms on read and write signals. The SMC
supports asynchronous burst read in page mode access for page size up to 32 bytes.
静态存储器控制器（SMC）
特点：
1． 可支持4个可选芯片
2． 每个可选芯片都支持64M地址空间
3． 8，16，32位数据总线
4． 支持字，半字，单字节传送
5． 单字节写入或单字节选择线路
6． 每个可选芯片都支持可编程的设置，脉冲和读信号等待时间
7． 每个可选芯片都支持可编程的设置，脉冲和写信号等待时间
8． 每个可选芯片都支持可编程的数据浮动时间
9． 兼容LCD模块
10． 支持外部等待功能
11． 支持在缓慢时钟模式下的自动开关功能
12． 支持在页面模式下的异步读功能，其中页面尺寸范围为4-32字节
描述：
静态存储器控制器（SMC）产生信号用来控制对外部存储器设备和外围设备的访问。这有4个可选芯片和一个26位的地址总线。那个32位的数据总线可以被配置为外部设备提供8位，16位，和32位的接口。单独读写信号也考虑到了直接存储器和外围接口，读和写信号波形是完全参数化的。
SMC也可以管理从外部设备而来的等待请求信号用于扩展通用访问。SMC也提供了一种自动的慢时钟模式。在慢时钟模式下，它是由用户编程提供的波形来控制，这种用户编程提供的波形是相对在读写信号上的慢率具体波形来说的。在能支持高达32字节页面的页面访问模式中，SMC也提供了对异步组数据的读功能。 28. SDRAM Controller (SDRAMC)
Rev: 2.0.1.1
28.1 Features
• Numerous Configurations Supported
– 2K, 4K, 8K Row Address Memory Parts
– SDRAM with Two or Four Internal Banks
– SDRAM with 16- or 32-bit Data Path
• Programming Facilities
– Word, Half-word, Byte Access
– Automatic Page Break When Memory Boundary Has Been Reached
– Multibank Ping-pong Access
– Timing Parameters Specified by Software
– Automatic Refresh Operation, Refresh Rate is Programmable
– Automatic Update of DS, TCR and PASR Parameters (Mobile SDRAM Devices)
• Energy-saving Capabilities
– Self-refresh, Power-down and Deep Power Modes Supported
– Supports Mobile SDRAM Devices
• Error Detection
– Refresh Error Interrupt
• SDRAM Power-up Initialization by Software
• CAS Latency of 1, 2, 3 Supported
• Auto Precharge Command Not Used
28.2 Description
The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the
interface to an external 16-bit or 32-bit SDRAM device. The page size supports ranges from
2048 to 8192 and the number of columns from 256 to 2048. It supports byte (8-bit), half-word
(16-bit) and word (32-bit) accesses.
The SDRAM Controller supports a read or write burst length of one location. It keeps track of the
active row in each bank, thus maximizing SDRAM performance, e.g., the application may be
placed in one bank and data in the other banks. So as to optimize performance, it is advisable to
avoid accessing different rows in the same bank.
The SDRAM controller supports a CAS latency of 1, 2 or 3 and optimizes the read access
depending on the frequency.
The different modes available - self-refresh, power-down and deep power-down modes - minimize
power consumption on the SDRAM device.
SDRAM控制器（SDRAMC）
特点：
1． 支持许多可配置选项-支持2K，4K，8K，行地址存储器部件
-支持带有2个或4个内部存储单元的SDRAM
-支持带有16位或32位的数据线的SDRAM
2．可编程的设备：-字，半字或字节访问
-支持在将到达存储器边界线时的自动页面中断功能
-支持多存储器的来回访问
-时间参数可由软件具体指定
-支持自动刷新操作，刷新率是可编程的
-支持DS，TCR和PASR参数（移动SDRAM设备）的自动升级
3．节能能力-支持自我自动刷新，电源故障，和深功率模式支持
-支持移动SDRAM设备
4．错误检测：-支持刷新错误中断
5．支持软件初始化SDRAM电源功能
6．支持1，2，3的CAS延迟
7．支持禁用预充电命令
描述：
SDRAM控制器扩展一个芯片存储器容量是通过为外部16位，32位的SDRAM设备提供接口来实现的。页面大小的支持范围是2048到8192，列的数目支持是从256到2048。它支持单字节（8位），半字（16位），和半字（32位）访问。SDRAM控制器支持读取或写入组长度的一个位置，它可以追踪在存储区内每个活跃的组，从而最大化的发挥SDRAM的性能，例如，应用程序可以设置放在一个存储区而数据可以放在另一个存储区。为了优化性能，避免访问处在同一存储区的不同组是明智的。
SDRAM控制器支持1，2或3个CAS延迟，也优化了依赖频率的读访问权限。
它也可以支持不同的模式：自我刷新模式，电源故障模式和深功率模式，也支持在SDRAM上的设备的最小功率消耗模式。 29. Ethernet MAC (MACB)
Rev: 1.1.2.5
29.1 Features
• Compatible with IEEE Standard 802.3
• 10 and 100 Mbit/s Operation
• Full- and Half-duplex Operation
• Statistics Counter Registers
• MII/RMII Interface to the Physical Layer
• Interrupt Generation to Signal Receive and Transmit Completion
• DMA Master on Receive and Transmit Channels
• Transmit and Receive FIFOs
• Automatic Pad and CRC Generation on Transmitted Frames
• Automatic Discard of Frames Received with Errors
• Address Checking Logic Supports Up to Four Specific 48-bit Addresses
• Supports Promiscuous Mode Where All Valid Received Frames are Copied to Memory
• Hash Matching of Unicast and Multicast Destination Addresses
• External Address Matching of Received Frames
• Physical Layer Management through MDIO Interface
• Half-duplex Flow Control by Forcing Collisions on Incoming Frames
• Full-duplex Flow Control with Recognition of Incoming Pause Frames and Hardware Generation
of Transmitted Pause Frames
• Support for 802.1Q VLAN Tagging with Recognition of Incoming VLAN and Priority Tagged
Frames
• Multiple Buffers per Receive and Transmit Frame
• Wake-on-LAN Support
• Jumbo Frames Up to 10240 bytes Supported
29.2 Description
The MACB module implements a 10/100 Ethernet MAC compatible with the IEEE 802.3 standard
using an address checker, statistics and control registers, receive and transmit blocks, and
a DMA interface.
The address checker recognizes four specific 48-bit addresses and contains a 64-bit hash register
for matching multicast and unicast addresses. It can recognize the broadcast address of all
ones, copy all frames, and act on an external address match signal.
The statistics register block contains registers for counting various types of events associated
with transmit and receive operations. These registers, along with the status words stored in the
receive buffer list, enable software to generate network management statistics compatible with
IEEE 802.3.
以太网介质访问控制（MACB）
特点：
1. 兼容IEEE802.3标准
2. 支持10M或100Mbit/s操作
3. 支持全双工或半双工操作
4. 集成静态计数器寄存器
5. 提供物理层的MII/RMII接口
6. 支持收到信号后或发送完成后的中断产生功能
7. 在接收器通道和发射器通道上集成DMA主机
8. 支持接收或发送FIFO
9. 支持发送帧上的自动填补和CRC产生功能
10. 支持自动丢弃收到的错误帧功能
11. 支持地址检测逻辑，支持高达4个专用的48位的地址线
12. 支持混乱模式,这种情况下,所有接收到的可用的帧都被复制到存储器区
13. 支持HASH值匹配的单播或组播目的地地址
14. 支持外部地址匹配接收到的帧
15. 扶持从MDIO接口而来的物理层管理器
16. 通过平息流入帧的冲突来控制半双工流
17. 通过流入的暂停帧和硬件产生的发送暂停帧的识别来控制全双工流
18. 通过确认流入的VLAN和优先级标记的帧来支持802.1Q VLAN协议
19. 为每个接收和发送的帧都有多重的缓冲区
20. 支持远程开机
21. 对于大型帧的支持高达10240字节
描述：
该MACB模块实现了一个10/100以太网MAC兼容，符合IEEE 802.3标准，使用一个地址检查，统计和控制寄存器，接收和发射块，集成一个DMA接口。
地址检查器确认4个专用的48位地址包括一个64位的hash寄存器，此寄存器用于匹配单播或组播地址。它可以确认所有的广播地址，复制所有的帧，产生一个外部地址用于匹配信号。
统计寄存器组包含了一些寄存器，这些寄存器用于计录各种类型的与发送和接收操作有关的事件数目。这些寄存器，与储存在接收缓冲区列表中的状态字一起，使得软件能够产生与IEEE 802.3兼容的网络管理统计数据。 完 预顶一下 非常支持！！其实我们内部有做部分的翻译工作，但是限于没有细细整理和斟酌，所以没有发布，谢谢shdzbsl及其同学的辛勤工作！谢谢！
以后我们可以多做交流！！ 另外，网站届时可能会组织一个AVR32的数据手册的翻译工作，欢迎大家的加入呢~~ 谢谢！可参考！ 谢谢,辛苦了 辛苦了！！！ 楼主辛苦了！
kingofkings 技术火腿（KoK）发布中文翻译怎么没有动静呀？就算有问题也总比没有的好！ 回复【22楼】kingofkings技术火腿（KoK）
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AVR32的数据手册的翻译工作???? 太给力了，翻译的不错，多谢！ 再顶楼主！ mark……
顶一个… 求完整版T T 貌似这款芯片最近很火啊 不错不错！！ 注： 原文件为：UC3AC_E.PDF
----楼主，文件已经失效，能把最新版本再传一下吗？
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