求verilog写的LCD1602驱动！ (amobbs.com 阿莫电子技术论坛) -

bjj9217 发表于 2008-5-2 00:21:53

求verilog写的LCD1602驱动！

哪位有LCD1602驱动，verilog写的。谢谢！

yiwang 发表于 2009-11-16 17:13:35

同求啊

tear086 发表于 2009-11-16 18:28:00

Altera DE2上的范例

LCD_Test.v
-----------------------------------------------------------------
// 9'h120 @ 9'h140 ` 9'h160
// ! 9'h121 A 9'h141 a 9'h161
// " 9'h122 B 9'h142 b 9'h162
// # 9'h123 C 9'h143 c 9'h163
// $ 9'h124 D 9'h144 d 9'h164
// % 9'h125 E 9'h145 e 9'h165
// & 9'h126 F 9'h146 f 9'h166
// ' 9'h127 G 9'h147 g 9'h167
// ( 9'h128 H 9'h148 h 9'h168
// ) 9'h129 I 9'h149 i 9'h169
// * 9'h12A J 9'h14A j 9'h16A
// + 9'h12B K 9'h14B k 9'h16B
// , 9'h12C L 9'h14C l 9'h16C
// - 9'h12D M 9'h14D m 9'h16D
// . 9'h12E N 9'h14E n 9'h16E
// / 9'h12F O 9'h14F o 9'h16F

// 0 9'h130 P 9'h150 p 9'h170
// 1 9'h131 Q 9'h151 q 9'h171
// 2 9'h132 R 9'h152 r 9'h172
// 3 9'h133 S 9'h153 s 9'h173
// 4 9'h134 T 9'h154 t 9'h174
// 5 9'h135 U 9'h155 u 9'h175
// 6 9'h136 V 9'h156 v 9'h176
// 7 9'h137 W 9'h157 w 9'h177
// 8 9'h138 X 9'h158 x 9'h178
// 9 9'h139 Y 9'h159 y 9'h179
// : 9'h13A Z 9'h15A z 9'h17A
// ; 9'h13B [ 9'h15B { 9'h17B
// < 9'h13C ￥ 9'h15C | 9'h17C
// = 9'h13D ] 9'h15D } 9'h17D
// > 9'h13E ^ 9'h15E → 9'h17E
// ? 9'h13F _ 9'h15F ← 9'h17F

module LCD_TEST ( // Host Side
iCLK,iRST_N,
// LCD Side
LCD_DATA,LCD_RW,LCD_EN,LCD_RS );
// Host Side
input iCLK,iRST_N;
// LCD Side
output LCD_DATA;
output LCD_RW,LCD_EN,LCD_RS;
// Internal Wires/Registers
reg LUT_INDEX;
reg LUT_DATA;
reg mLCD_ST;
reg mDLY;
reg mLCD_Start;
reg mLCD_DATA;
reg mLCD_RS;
wire mLCD_Done;

parameter LCD_INTIAL = 0;
parameter LCD_LINE1 = 5;
parameter LCD_CH_LINE = LCD_LINE1+16;
parameter LCD_LINE2 = LCD_LINE1+16+1;
parameter LUT_SIZE = LCD_LINE1+32+1;

always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
LUT_INDEX <= 0;
mLCD_ST <= 0;
mDLY <= 0;
mLCD_Start <= 0;
mLCD_DATA <= 0;
mLCD_RS <= 0;
end
else
begin
if(LUT_INDEX<LUT_SIZE)
begin
case(mLCD_ST)
0: begin
mLCD_DATA <= LUT_DATA;//
mLCD_RS <= LUT_DATA; //
mLCD_Start <= 1;
mLCD_ST <= 1;
end
1: begin
if(mLCD_Done)
begin
mLCD_Start <= 0;
mLCD_ST <= 2;
end
end
2: begin
if(mDLY<18'h3FFFE)
mDLY <= mDLY+1;
else
begin
mDLY <= 0;
mLCD_ST <= 3;
end
end
3: begin
LUT_INDEX <= LUT_INDEX+1;
mLCD_ST <= 0;
end
endcase
end
end
end

always
begin
case(LUT_INDEX)
// Initial
LCD_INTIAL+0: LUT_DATA <= 9'h038;
LCD_INTIAL+1: LUT_DATA <= 9'h00C;
LCD_INTIAL+2: LUT_DATA <= 9'h001;
LCD_INTIAL+3: LUT_DATA <= 9'h006;
LCD_INTIAL+4: LUT_DATA <= 9'h080;
// Line 1
LCD_LINE1+0: LUT_DATA <= 9'h148; // Hello!
LCD_LINE1+1: LUT_DATA <= 9'h165;
LCD_LINE1+2: LUT_DATA <= 9'h16C;
LCD_LINE1+3: LUT_DATA <= 9'h16C;
LCD_LINE1+4: LUT_DATA <= 9'h16F;
LCD_LINE1+5: LUT_DATA <= 9'h121;
LCD_LINE1+6: LUT_DATA <= 9'h15C;
LCD_LINE1+7: LUT_DATA <= 9'h120;
LCD_LINE1+8: LUT_DATA <= 9'h120;
LCD_LINE1+9: LUT_DATA <= 9'h120;
LCD_LINE1+10: LUT_DATA <= 9'h120;
LCD_LINE1+11: LUT_DATA <= 9'h120;
LCD_LINE1+12: LUT_DATA <= 9'h120;
LCD_LINE1+13: LUT_DATA <= 9'h120;
LCD_LINE1+14: LUT_DATA <= 9'h120;
LCD_LINE1+15: LUT_DATA <= 9'h120;
// Change Line
LCD_CH_LINE: LUT_DATA <= 9'h0C0;
// Line 2
LCD_LINE2+0: LUT_DATA <= 9'h120; //
LCD_LINE2+1: LUT_DATA <= 9'h120;
LCD_LINE2+2: LUT_DATA <= 9'h120;
LCD_LINE2+3: LUT_DATA <= 9'h120;
LCD_LINE2+4: LUT_DATA <= 9'h120;
LCD_LINE2+5: LUT_DATA <= 9'h120;
LCD_LINE2+6: LUT_DATA <= 9'h120;
LCD_LINE2+7: LUT_DATA <= 9'h120;
LCD_LINE2+8: LUT_DATA <= 9'h120;
LCD_LINE2+9: LUT_DATA <= 9'h120;
LCD_LINE2+10: LUT_DATA <= 9'h120;
LCD_LINE2+11: LUT_DATA <= 9'h120;
LCD_LINE2+12: LUT_DATA <= 9'h120;
LCD_LINE2+13: LUT_DATA <= 9'h120;
LCD_LINE2+14: LUT_DATA <= 9'h120;
LCD_LINE2+15: LUT_DATA <= 9'h120;
default: LUT_DATA <= 9'h000;
endcase
end

LCD_Controller u0 ( // Host Side
.iDATA(mLCD_DATA),
.iRS(mLCD_RS),
.iStart(mLCD_Start),
.oDone(mLCD_Done),
.iCLK(iCLK),
.iRST_N(iRST_N),
// LCD Interface
.LCD_DATA(LCD_DATA),
.LCD_RW(LCD_RW),
.LCD_EN(LCD_EN),
.LCD_RS(LCD_RS) );

endmodule
-----------------------------------------------------------------

LCD_Controller.v
-----------------------------------------------------------------
module LCD_Controller ( // Host Side
iDATA,iRS,
iStart,oDone,
iCLK,iRST_N,
// LCD Interface
LCD_DATA,
LCD_RW,
LCD_EN,
LCD_RS );
// CLK
parameter CLK_Divide = 16;

// Host Side
input iDATA;
input iRS,iStart;
input iCLK,iRST_N;
output reg oDone;
// LCD Interface
output LCD_DATA;
output reg LCD_EN;
output LCD_RW;
output LCD_RS;
// Internal Register
reg Cont;
reg ST;
reg preStart,mStart;

/////////////////////////////////////////////
// Only write to LCD, bypass iRS to LCD_RS
assign LCD_DATA = iDATA;
assign LCD_RW = 1'b0;
assign LCD_RS = iRS;
/////////////////////////////////////////////

always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
oDone <= 1'b0;
LCD_EN <= 1'b0;
preStart<= 1'b0;
mStart <= 1'b0;
Cont <= 0;
ST <= 0;
end
else
begin
////// Input Start Detect ///////
preStart<= iStart;
if({preStart,iStart}==2'b01)
begin
mStart <= 1'b1;
oDone <= 1'b0;
end
//////////////////////////////////
if(mStart)
begin
case(ST)
0: ST <= 1; // Wait Setup
1: begin
LCD_EN <= 1'b1;
ST <= 2;
end
2: begin
if(Cont<CLK_Divide)
Cont <= Cont+1;
else
ST <= 3;
end
3: begin
LCD_EN <= 1'b0;
mStart <= 1'b0;
oDone <= 1'b1;
Cont <= 0;
ST <= 0;
end
endcase
end
end
end

endmodule
-----------------------------------------------------------------

feiafei043 发表于 2010-4-7 11:33:11

谢谢 tear086 .COM 缺氧

页: [1]

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求verilog写的LCD1602驱动！