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本帖最后由 YaphetS 于 2012-3-30 13:03 编辑
新论坛第一帖,申请酷帖。
最近忙着如何在DE2上实现驱动VGA,终于在成功之后,将代码进一步规范,完善之后发布,过程中参考了Xiaomagee ,AKuei2和cnblog上刘强的日志。
看下效果图
先上传下我参考的资料
第一篇:
谈谈VGA的时序
现在简单分析下,VGA显示分为行显示和场显示,说白点就是X和Y轴的显示,我们需要关心的图2中的c段和q段,这两段的重合之处便是显示器显示
的阶段,这个阶段显示器从RGB口读取电压显示器AD转换为色彩显示,其余时序段根据名字就能知道作用,尤其关心的是电平被拉低的那一段,因为
整个时序中只有那一段被拉低。
所以我们要做的就是模拟时序,直到重合段写入RGB数据。
第二篇
显示驱动芯片 ADV7123
这是DE2中ADV7123的原理图,关于这个芯片的资料我整理出来了
第三篇
代码篇
代码写的浅显易懂,不同于我参考的的代码,基本上是仿顺序,仿时序写的,注释也还好,看代码肯定,比我说的好。
先看下RTL视图
sync_module- module sync_module
- (
- VGA_CLK, RSTn,
- VGA_HS, VGA_VS,
- VGA_BLANKn, VGA_SYNCn,
- VGA_X, VGA_Y,
- VGA_ACT,
- DAC_CLK
- );
-
- input VGA_CLK, RSTn;
- output VGA_HS, VGA_VS;
- output VGA_BLANKn, VGA_SYNCn;
- output[11:0] VGA_X, VGA_Y; // MAX 4096
- output VGA_ACT; // When the VGA is ready to displayy that means in the active area Set to 1
- output DAC_CLK;
- /**************** 800*600@60HZ ********************/
- //Horizontal parameter
- parameter H_FRONT = 40; // d
- parameter H_SYNC = 128; // a
- parameter H_BACK = 88; // b
- parameter H_ACT = 800; // c
- parameter H_BLANK = H_FRONT + H_SYNC + H_BACK;
- parameter H_TOTAL = H_BLANK + H_ACT;
- //Vertical parameter
- parameter V_FRONT = 1; // r
- parameter V_SYNC = 4; // o
- parameter V_BACK = 23; // p
- parameter V_ACT = 600; // q
- parameter V_BLANK = V_FRONT + V_SYNC + V_BACK;
- parameter V_TOTAL = V_BLANK + V_ACT;
- /**************************************************/
- //ADV7123
- assign DAC_CLK = VGA_CLK;
- assign VGA_BLANKn = VGA_HS && VGA_VS;
- assign VGA_SYNCn = 1'b0; //If the SOG is not enable, SYNC should be set to 0;
- //Horizontal Generator
- reg[11:0] H_Count;
- reg VGA_HSr;
- reg[11:0] VGA_Xr;
- reg VGA_HACT;
- always @ (posedge VGA_CLK or negedge RSTn)
- begin
- if(!RSTn)
- begin
- VGA_HSr <= 1'b0;
- VGA_HACT <= 1'b0;
- VGA_Xr <= 12'd0;
- H_Count <= 12'd0;
- end
- else
- begin
- if (H_Count == H_TOTAL)
- H_Count <= 12'd0;
- else
- H_Count <= H_Count + 1'b1;
-
- // Generate SYNC
- if (H_Count <= H_SYNC)
- VGA_HSr <= 1'b0;
- else
- VGA_HSr <= 1'b1;
-
- // Define the active area
- if ((H_Count > (H_SYNC+H_BACK))&&(H_Count <= (H_SYNC+H_BACK+H_ACT)))
- begin
- VGA_HACT <= 1'b1;
- VGA_Xr <= H_Count - (H_SYNC+H_BACK+1); // X Address range 0-H_ACT
- end
- else
- begin
- VGA_HACT <= 1'b0;
- VGA_Xr <= 12'd0;
- end
- end
- end
- assign VGA_HS = VGA_HSr;
- assign VGA_X = VGA_Xr;
- //Vertical Generator
- reg[11:0] V_Count;
- reg VGA_VSr;
- reg[11:0] VGA_Yr;
- reg VGA_VACT;
- always @ (posedge VGA_CLK or negedge RSTn)
- begin
- if(!RSTn)
- begin
- VGA_VSr <= 1'b0;
- VGA_VACT <= 1'b0;
- VGA_Yr <= 12'd0;
- V_Count <= 12'd0;
- end
- else
- begin
- if (V_Count == V_TOTAL)
- V_Count <= 12'd0;
- else if(H_Count == H_TOTAL)
- V_Count <= V_Count + 1'b1;
-
- // Generate SYNC
- if (V_Count <= V_SYNC)
- VGA_VSr <= 1'b0;
- else
- VGA_VSr <= 1'b1;
-
- // Define the active area
- if ((V_Count > (V_SYNC+V_BACK))&&(V_Count <= (V_SYNC+V_BACK+V_ACT)))
- begin
- VGA_VACT <= 1'b1;
- VGA_Yr <= V_Count - (V_SYNC+V_BACK); // Y Address range 0-V_ACT
- end
- else
- begin
- VGA_VACT <= 1'b0;
- VGA_Yr <= 12'd0;
- end
- end
- end
- assign VGA_VS = VGA_VSr;
- assign VGA_Y = VGA_Yr;
- assign VGA_ACT = VGA_HACT&&VGA_VACT;
- endmodule
复制代码 vga_control_module- module vga_control_module
- (
- VGA_CLK, RSTn,
- VGA_X, VGA_Y,
- VGA_ACT,
- VGA_R, VGA_G, VGA_B
- );
- input VGA_CLK, RSTn;
- input[11:0] VGA_X, VGA_Y;
- input VGA_ACT;
- output[9:0] VGA_R, VGA_G, VGA_B;
- //Pattern Generator
- reg[9:0] VGA_Rr, VGA_Gr, VGA_Br;
- always @ (posedge VGA_CLK or negedge RSTn)
- begin
- if (!RSTn)
- begin
- VGA_Rr <= 0;
- VGA_Gr <= 0;
- VGA_Br <= 0;
- end
- else
- begin
- VGA_Rr <= (VGA_Y < 10'd100) ? 10'd1023 :
- (VGA_Y>=10'd100 && VGA_Y<=10'd200) ? 10'd896:
- (VGA_Y>=10'd200 && VGA_Y<=10'd300) ? 10'd768:
- (VGA_Y>=10'd300 && VGA_Y<=10'd400) ? 10'd512:
- (VGA_Y>=10'd400 && VGA_Y<=10'd500) ? 10'd256:
- 128;
-
- VGA_Gr <= (VGA_X < 10'd100) ? 10'd128 :
- (VGA_X>=10'd100 && VGA_X<=10'd200) ? 10'd256:
- (VGA_X>=10'd200 && VGA_X<=10'd300) ? 10'd384:
- (VGA_X>=10'd300 && VGA_X<=10'd400) ? 10'd512:
- (VGA_X>=10'd400 && VGA_X<=10'd500) ? 10'd640:
- (VGA_X>=10'd500 && VGA_X<=10'd600) ? 10'd768:
- (VGA_X>=10'd600 && VGA_X<=10'd700) ? 10'd896:
- 1023;
-
- VGA_Br <= (VGA_Y < 10'd100) ? 10'd128 :
- (VGA_Y>=10'd100 && VGA_Y<=10'd200) ? 10'd256:
- (VGA_Y>=10'd200 && VGA_Y<=10'd300) ? 10'd512:
- (VGA_Y>=10'd300 && VGA_Y<=10'd400) ? 10'd768:
- (VGA_Y>=10'd400 && VGA_Y<=10'd500) ? 10'd896:
- 1023;
- end
- end
- assign VGA_R = VGA_Rr;
- assign VGA_G = VGA_Gr;
- assign VGA_B = VGA_Br;
- endmodule
复制代码 vga_module TOP- module vga_module
- (
- CLK_50M, RSTn,
- VGA_HS, VGA_VS,
- VGA_BLANKn, VGA_SYNCn,
- DAC_CLK,
- VGA_R, VGA_G, VGA_B
- );
- input CLK_50M, RSTn;
- output VGA_HS, VGA_VS;
- output VGA_BLANKn, VGA_SYNCn;
- output DAC_CLK;
- output[9:0] VGA_R, VGA_G, VGA_B;
- wire VGA_CLK;
- pll_module U1
- (
- .inclk0(CLK_50M),
- .c0(VGA_CLK)
- );
- wire[11:0] VGA_X, VGA_Y;
- wire VGA_ACT;
-
- sync_module U2
- (
- .VGA_CLK(VGA_CLK),
- .RSTn(RSTn),
- .VGA_HS(VGA_HS),
- .VGA_VS(VGA_VS),
- .VGA_BLANKn(VGA_BLANKn),
- .VGA_SYNCn(VGA_SYNCn),
- .VGA_X(VGA_X),
- .VGA_Y(VGA_Y),
- .VGA_ACT(VGA_ACT),
- .DAC_CLK(DAC_CLK)
- );
- vga_control_module U3
- (
- .VGA_CLK(VGA_CLK),
- .RSTn(RSTn),
- .VGA_X(VGA_X),
- .VGA_Y(VGA_Y),
- .VGA_ACT(VGA_ACT),
- .VGA_R(VGA_R),
- .VGA_G(VGA_G),
- .VGA_B(VGA_B)
- );
- endmodule
复制代码 最后上传下当时的情景
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